HT46R94 datasheet(21/62 Pages) HOLTEK

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HT46R94

Rev. 1.10

November 5, 2008

Timer Control Register

- TMR0C, TMR1C

The flexible features of the Holtek microcontroller Timer/

Event Counters enable them to operate in three different

modes, the options of which are determined by the con-

tents of their respective control register. The device con-

tains two timer control registers known as TMR0C and

TMR1C. It is the timer control register together with its

corresponding timer registers that control the full opera-

tion of the Timer/Event Counters. Before the timers can

be used, it is essential that the appropriate timer control

its correct operation, a process that is normally carried

out during program initialisation.

To choose which of the three modes the timer is to oper-

ate in, either in the timer mode, the event counting mode

or the Pulse Width Measurement mode, bits 7 and 6 of

the Timer Control Register, which are known as the bit

pair T0M1/T0M0 or T1M1/T1M0 respectively, depend-

ing upon which timer is used, must be set to the required

logic levels. The timer-on bit, which is bit 4 of the Timer

Control Register and known as T0ON or T1ON, depend-

ing upon which timer is used, provides the basic on/off

control of the respective timer. Setting the bit high allows

the counter to run, clearing the bit stops the counter. The

Timer/Event Counters also contains a prescaler func-

tion, with bits 0~2 of the associated Timer Control Reg-

ister determining the division ratio of the input clock. The

prescaler bit settings have no effect if an external clock

source is used. If the timer is in the Event Count or Pulse

Width Measurement mode, the active transition edge

level type is selected by the logic level of bit 3 of the

Timer Control Register which is known as T0E or T1E,

depending upon which timer is used.

Configuring the Timer Mode

In this mode, the Timer/Event Counters can be utilised

to measure fixed time intervals, providing an internal in-

terrupt signal each time the counter overflows. To oper-

ate in this mode, the Operating Mode Select bit pair in

the appropriate Timer Control Register must be set to

the correct value as shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode, a choice of internal clocks can be used as

the Timer/Event Counter clock, depending upon which

Timer/Event Counter is being used. However, this clock

source is further divided by a prescaler, the value of

which is determined by the Prescaler Rate Select bits,

which are bits 0~2 in the respective Timer Control Reg-

ister. After the other bits in the Timer Control Register

have been setup, the enable bit, which is bit 4 of the

Timer Control Register, can be set high to enable the

Timer/Event Counter to run. Each time an internal clock

cycle occurs, the Timer/Event Counter increments by

one. When it is full and overflows, an interrupt signal is

generated and the Timer/Event Counter will reload the

value already loaded into the preload register and con-

tinue counting. The interrupt can be disabled by ensur-

ing that the Timer/Event Counter Interrupt Enable bit in

the Interrupt Control Register, is reset to zero.

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pins, can be re-

corded by the Timer/Event Counters. To operate in this

mode, the Operating Mode Select bit pair in the appro-

priate Timer Control Register must be set to the correct

value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode the external timer pins are used as the

Timer/Event Counter clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

appropriate Timer Control Register have been setup,

the enable bit, which is bit 4 of the Timer Control Regis-

ter, can be set high to enable the Timer/Event Counter to

run. If the Active Edge Select bit, which is bit 3 of the ap-

propriate Timer Control Register, is low, the

Timer/EventCounter will increment each time the asso-

ciated external timer pin receives a low to high transi-

tion. If the Active Edge Select bit is high, the

Timer/Event Counter will increment each time the exter-

nal timer pin receives a high to low transition. When it is

full and overflows, an interrupt signal is generated and

the Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the asso-

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

T i m e r + 2

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Chart

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