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HT46R92 датащи(PDF) 35 Page - Holtek Semiconductor Inc |
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HT46R92 датащи(HTML) 35 Page - Holtek Semiconductor Inc |
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35 / 61 page ![]() HT46R92 Rev. 1.10 35 November 5, 2008 Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI , and the corresponding timer interrupt enable bit, ETI in the INTC0 register must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter interrupt request flag, TF in INTC0, is set, a situation that will occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H will take place for Timer/Event Counter. When the interrupt is serviced, the timer interrupt request flag, TF, will be au- tomatically reset and the EMI bit will be automatically cleared to disable other interrupts. Time Base Interrupt For a Time Base interrupt to occur, the global interrupt enable bit, EMI, in the INTC0 register, and the Time Base interrupt enable bit, ETBI, in the INTC0 register must first be set. An actual Time Base interrupt will take place when the Time Base request flag, TBF in INTC0 is set, a situation that will occur when the Time Base over- flows. When the interrupt is enabled, the stack is not full, and a Time Base overflow occurs, a subroutine call to the Time Base vector location at 0CH will take place. When the interrupt is serviced, the Time Base interrupt request flag, TBF, will be automatically reset and the EMI bit will be automatically cleared to disable other in- terrupts. A/D Interrupt For an A/D interrupt to occur, the global interrupt enable bit, EMI, and the corresponding interrupt enable bit, EADI, must be first set. An actual A/D interrupt will take place when the A/D converter request flag, ADF in the INTC1 register is set, a situation that will occur when an A/D conversion process has completed. When the inter- rupt is enabled, the stack is not full and an A/D conver- sion process finishes execution, a subroutine call to the A/D interrupt vector at location 10H, will take place. When the interrupt is serviced, the A/D interrupt request flag, ADF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bits, a requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC0 or INTC1 register until the corre- sponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the ²CALL subroutine ² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well con- trolled, the original control sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. C l o c k S o u r c e C o n f i g u r a t i o n O p t i o n f S Y S / 4 W D T O s c i l l a t o r R T C O s c i l l a t o r 8 - S t a g e P r e s c a l e r ( 1 / 2 ~ 1 / 2 5 6 ) f S T B 0 ~ T B 2 ¸ 1 6 T i m e B a s e I n t e r r u p t ( f S / 3 2 ~ f S / 4 0 9 6 ) T i m e B a s e C l o c k S o u r c e S e l e c t Time Base Interrupt |
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