Data Sheet

AD5111/AD5113/AD5115

Rev. 0 | Page 9 of 24

INTERFACE TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Description

50

MHz

Clock frequency

25

MHz

25

ns

CS setup time

10

ns

CLK low time

20

ns

10

ns

CLK high time

20

ns

15

ns

U/D setup time

6

ns

U/D hold time

20

ns

CS rise to CLK hold time

40

ns

15

ns

CS rising edge to next CLK ignored

12

ns

U/D minimum pulse time

24

ns

12

ns

U/D rise to CLK falling edge

1

µs

Minimum CS time

15

50

ms

Memory program time

50

µs

Power-on EEPROM restore time

1

EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.

2

TIMING DIAGRAMS

CLK

CS

U/D

Figure 2. Increment/Decrement Mode Timing

DATA

EEPROM

NEW DATA

CLK

CS

U/D

Figure 3. Storage Mode Timing

CS

CLK

U/D

Figure 4. Shutdown Mode Timing