Data Sheet

AD5110/AD5112/AD5114

Rev. 0 | Page 9 of 28

INTERFACE TIMING SPECIFICATIONS

Table 5.

Parameter1

Test Conditions/

Comments

Min

Typ

Max

Unit

Description

fSCL2

Standard mode

100

kHz

Serial clock frequency

Fast mode

400

kHz

Standard mode

4.0

µs

Fast mode

0.6

µs

Standard mode

4.7

µs

Fast mode

1.3

µs

Standard mode

250

ns

Fast mode

100

ns

Standard mode

0

3.45

µs

Fast mode

0

0.9

µs

Standard mode

4.7

µs

Fast mode

0.6

µs

Standard mode

4

µs

Fast mode

0.6

µs

Standard mode

4.7

µs

condition

Fast mode

1.3

µs

Standard mode

4

µs

Fast mode

0.6

µs

Standard mode

1000

ns

Fast mode

300

ns

Standard mode

300

ns

Fast mode

300

ns

Standard mode

1000

ns

Fast mode

300

ns

Standard mode

1000

ns

condition and after an acknowledge bit.

Fast mode

300

ns

Standard mode

300

ns

Fast mode

300

ns

tSP3

Fast mode

0

50

ns

Pulse width of suppressed spike

15

50

ms

Memory program time

50

µs

Power-on EEPROM restore time

25

µs

Reset EEPROM restore time

1

Maximum bus capacitance is limited to 400 pF.

2

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

3

Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.

4

EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.

5