Technical Note

9/11

BD5650AFVM

www.rohm.com

2011.11 - Rev.B

© 2011 ROHM Co., Ltd. All rights reserved.

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Operation Notes

1) Absolute maximum ratings

Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may

result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or

open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when

use of the IC in a special mode w here the absolute maximum ratings may be exceeded is anticipated.

2) GND potential

Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND

pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. As an exception,

the circuit design allows voltages up to -0.3 V to be applied to the ICT pin.

3) Setting of heat

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating

conditions.

4) Pin short and mistake fitting

Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result

in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by

the presence of a foreign object may result in damage to the IC.

5) Actions in strong magnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to

malfunction.

6) Mutual impedance

Power supply and ground wiring should reflect consideration of the need to lower mutual impedance and minimize

ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating

inductance and capacitance).

7) Regarding input pin of the IC

This IC is a monolithic IC which (as shown is Fig-1)has P

formed from this P layer of each pin. For example, the relation between each potential is as follows,

○

(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)

○

(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)

Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by

which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input

pin.

Although the circuit design allows voltages up to -0.3 V to be applied to the ICT pin, voltages lower than this may cause

the behavior described above. Use caution when designing the circuit.

Parasitic diode

GND

B

P

P substrate

Parasitic diode

Fig.20

Simplified structure of a Bipolar IC

P substrate

Parasitic diode

GND

N

P

＋

Resistance

Ｎ

Transistor (NPN)

Other adjacent components

(PinB)

(PinA)

P

＋

GND

N

N

B

C

E

N

(PinA)

(PinB)

GND

GND

Parasitic diode

C

E