CBTL04DP211

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 1 — 30 March 2011

4 of 17

NXP Semiconductors

CBTL04DP211

DisplayPort 2 : 1 multiplexer

7.

Pinning information

7.1 Pinning

7.2 Pin description

Fig 2.

Pin configuration for HVQFN32

002aag019

Transparent top view

IN1_1+

27

1

OUT_0+

IN1_1-

26

2

OUT_0-

IN2_0+

25

3

IN2_0-

24

4

OUT_1+

IN2_1+

23

5

OUT_1-

IN2_1-

22

6

AUX+

GND

21

7

AUX-

20

8

HPD_IN

AUX1+

19

9

AUX1-

18

10

GPU_SEL

HPD_1

17

11

n.c.

CBTL04DP211BS

Table 3.

Pin description

Symbol

Pin

Type

Description

GPU_SEL

10

3.3 V CMOS

single-ended input

Selection for Main Link and Hot Plug Detect

signals between two multiplexer/switch paths.

When HIGH, path 2 is connected to its

corresponding I/O. When LOW, path 1 is

connected to its corresponding I/O.

AUX_SEL

32

3.3 V CMOS

single-ended input

Selects between AUX paths. When HIGH, AUX2

(path 2) input is connected to AUX output. When

LOW, AUX1 (path 1) input is connected to AUX

output.

IN1_0+

31

differential I/O

Two bidirectional high-speed differential pairs for

DisplayPort Main Link signals, path 1.

IN1_0



30

differential I/O

IN1_1+

27

differential I/O

IN1_1



26

differential I/O

IN2_0+

25

differential I/O

Two bidirectional high-speed differential pairs for

DisplayPort Main Link signals, path 2.

IN2_0



24

differential I/O

IN2_1+

23

differential I/O

IN2_1



22

differential I/O