17

ICS9LPRS464

System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss

System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs

1377A—04/07/08

SMBus Table: Byte Count Register

Byte 8

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

-

BC7

RW

0

Bit 6

-

BC6

RW

0

Bit 5

-

BC5

RW

0

Bit 4

-

BC4

RW

0

Bit 3

-

BC3

RW

1

Bit 2

-

BC2

RW

0

Bit 1

-

BC1

RW

0

Bit 0

-

BC0

RW

1

SMBus Table: REF2, 48MHz Output Strength Control and ATIG Frequency Select Register

Byte 9

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

54

REF2Str

REF2 Strength Control

RW

1X

2X

1

Bit 6

7

48MHz_1Str

48MHz_1 Strength Control

RW

1X

2X

1

Bit 5

6

48MHz_0Str

48MHz_0 Strength Control

RW

1X

2X

1

Bit 4

0

Bit 3

-

ATIG FS3

ATIG Freq Select Bit 3

RW

0

Bit 2

-

ATIG FS2

ATIG Freq Select Bit 2

RW

0

Bit 1

-

ATIG FS1

ATIG Freq Select Bit 1

RW

0

Bit 0

-

ATIG FS0

ATIG Freq Select Bit 0

RW

0

SMBus Table: PLLs M/N Programming Enable and REF1, REF0 Output Strength Control Register

Byte 10

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

-

M/N_EN

PLLs M/N Programming Enable

RW

Disable

Enable

0

Bit 6

55

REF1Str

REF1 Strength Control

RW

1X

2X

1

Bit 5

56

REF0Str

REF0 Strength Control

RW

1X

2X

1

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

SMBus Table: CPU PLL VCO Frequency Control Register

Byte 11

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

-

N Div8

N Divider Prog bit 8

RW

X

Bit 6

-

N Div 9

N Divider Prog bit 9

RW

X

Bit 5

-

M Div5

RW

X

Bit 4

-

M Div4

RW

X

Bit 3

-

M Div3

RW

X

Bit 2

-

M Div2

RW

X

Bit 1

-

M Div1

RW

X

Bit 0

-

M Div0

RW

X

SMBus Table: CPU PLL VCO Frequency Control Register

Byte 12

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

-

N Div7

RW

X

Bit 6

-

N Div6

RW

X

Bit 5

-

N Div5

RW

X

Bit 4

-

N Div4

RW

X

Bit 3

-

N Div3

RW

X

Bit 2

-

N Div2

RW

X

Bit 1

-

N Div1

RW

X

Bit 0

-

N Div0

RW

X

The decimal representation of

M and N Divier in Byte 11 and

12 will configure the VCO

frequency. Default at power

up = latch-in or Byte 0 Rom

table. VCO Frequency =

14.318 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]

M Divider Programming bits

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Byte Count Programming b(7:0)

Writing to this register will

congiure how many bytes will

be read back, default is 9

bytes.

See Table 3: ATIG

Frequency Selection Table

N Divider Programming b(7:0)

The decimal representation of

M and N Divier in Byte 11 and

12 will configure the VCO

frequency. Default at power

up = latch-in or Byte 0 Rom

table. VCO Frequency =

14.318 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]