56-pin CK505 w/Fully Integrated Voltage Regulator

1124D—02/26/09

Advance Information

ICS9LPR502

56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

5

Datasheet

SSOP/TSSOP Pin Description (Continued)

Fully Integrated Regulator Connection for Desktop/Mobile Applications

PIN #

PIN NAME

TYPE

DESCRIPTION

48

CK_PWRGD/PD#

IN

Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode

49

FSLB/TEST_MODE

IN

3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS

and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider

mode while in test mode. Refer to Test Clarification Table.

50

GNDREF

PWR

Ground pin for crystal oscillator circuit

51

X2

OUT

Crystal output, nominally 14.318MHz.

52

X1

IN

Crystal input, Nominally 14.318MHz.

53

VDDREF

PWR

Power pin for the REF outputs, 3.3V nominal.

54

REF0/FSLC/TEST_SEL

I/O

3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.

Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched

input to enable test mode. Refer to Test Clarification Table.

55

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

56

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

1.05V to 3.3V

(+/-5%)

NC

PIN 40

CPU_IO Decoupling

Network

96_IO Decoupling

Network

ICS9LPR502

ICS9LPRS502

VDDCPU_IO, Pin 41

VDDSRC_IO Pin 37, 26

VDDPLL3_IO, Pin 20

VDD96_IO, Pin 12

PLL3_IO Decoupling

Network

SRC_IO Decoupling

Network