ICS841S012DI datasheet(11/22 Pages) IDT

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ICS841S012DKI REVISION A JULY 20, 2009

ICS841S012DI Data Sheet

CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER

FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in

Figure 3. The XTAL_OUT pin can be left floating. The

input edge rate can be as slow as 10ns. For LVCMOS signals, it

is recommended that the amplitude be reduced from full swing to

half swing in order to prevent signal interference with the power

rail and to reduce noise. This configuration requires that the output

impedance of the driver (Ro) plus the series resistance (Rs)

equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half.

This can be done in one of two ways. First, R1 and R2 in parallel

should equal the transmission line impedance. For most 50

applications, R1 and R2 can be 100

Ω. This can also be

accomplished by removing R1 and making R2 50

Ω. By overdriving

the crystal oscillator, the device will be functional, but note the

device performance is guaranteed by using a quartz crystal.

Zo = 50

VDD

Zo = Ro + Rs

VDD

XTAL_IN

XTAL_OUT

.1uf

CRYSTAL INPUT INTERFACE

The ICS841S012DI has been characterized with 18pF parallel

resonant crystals. The capacitor values shown in

Figure 2 below

were determined using a 25MHz, 18pF parallel resonant crystal

FIGURE 2. CRYSTAL INPUT INTERFACE

and were chosen to minimize the ppm error. NOTE: External tun-

ing capacitors must be used for proper operations.

XTAL_IN

XTAL_OUT

18pF Parallel Crystal

15p

22p

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