ICS9DB401C

Four Output Differential Buffer for PCI Express

ICS9DB401C

REV E 03/18/08

Four Output Differential Buffer for PCI Express

DATASHEET

1

Description

Output Features

The 9DB401C is a DB400 Version 2.0 Yellow Cover part with

PCI Express support. It can be used in PC or embedded

systems to provide outputs that have low cycle-to-cycle jitter

(50ps), low output-to-output skew (100ps), and are PCI Express

gen 1 compliant. The 9DB401C supports a 1 to 4 output

configuration, taking a spread or non spread differential HCSL

input from a CK410(B) main clock such as 954101 and

932S401, or any other differential HCSL pair. 9DB401C can

generate HCSL or LVDS outputs from 50 to 200MHz in PLL

mode or 0 to 400Mhz in bypass mode. There are two de-jittering

modes available selectable through the HIGH_BW# input pin,

high bandwidth mode provides de-jittering for spread inputs and

low bandwidth mode provides extra de-jittering for non-spread

inputs. The SRC_STOP#, PD#, and OE real-time input pins

provide completely programmable power management control.

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4 - 0.7V HCSL or LVDS differential output pairs

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Supports zero delay buffer mode and fanout mode

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Bandwidth programming available

Funtional Block Diagram

Key Specifications

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Outputs cycle-cycle jitter: < 50ps

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Outputs skew: < 50ps

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Extended frequency range in bypass mode:

Revision B: up to 333.33MHz

Revision C: up to 400MHz

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Real-time PLL lock detect output pin

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28-pin SSOP/TSSOP package

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Available in RoHS compliant packaging

Features/Benefits

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Spread spectrum modulation tolerant, 0 to -0.5% down

spread and +/- 0.25% center spread

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Supports undriven differential outputs in PD# and

SRC_STOP# modes for power management.

STOP

LOGIC

SRC_IN

SRC_IN#

DIF(3:0))

CONTROL

LOGIC

BYPASS#/PLL

SDATA

SCLK

PD

SPREAD

COMPATIBLE

PLL

4

IREF

OE(3:0)

4

M

U

X

Note: Polarities shown for OE_INV = 0.