1681C—08/26/10

9FG430

Four Output Differential Frequency Generator for PCIe Gen3 and QPI

3

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

XIN/CLKIN

IN

Crystal input or Reference Clock input

2

X2

OUT

Crystal output, Nominally 14.318MHz

3

VDD

PWR

Power supply, nominal 3.3V

4

GND

PWR

Ground pin.

5

REFOUT

OUT

Reference Clock output

6

vFS2

IN

Frequency select pin. This pin has an internal 120k pull down resistor

7

DIF_3

OUT

0.7V differential true clock output

8

DIF_3#

OUT

0.7V differential Complementary clock output

9

VDD

PWR

Power supply, nominal 3.3V

10

GND

PWR

Ground pin.

11

DIF_2

OUT

0.7V differential true clock output

12

DIF_2#

OUT

0.7V differential Complementary clock output

13

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

14

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

15

DIF_STOP#

IN

Active low input to stop differential output clocks.

16

vSPREAD

IN

Asynchronous, active high input to enable spread spectrum functionality. This pin

has a 120Kohm pull down resistor.

17

^SEL14M_25M#

IN

Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm

pull up resistor.

1 = 14.31818 MHz, 0 = 25 MHz

18

DIF_1#

OUT

0.7V differential Complementary clock output

19

DIF_1

OUT

0.7V differential true clock output

20

GND

PWR

Ground pin.

21

VDD

PWR

Power supply, nominal 3.3V

22

DIF_0#

OUT

0.7V differential Complementary clock output

23

DIF_0

OUT

0.7V differential true clock output

24

vFS1

IN

Frequency select pin.

25

vFS0

IN

Frequency select pin.

26

IREF

OUT

This pin establishes the reference for the differential current-mode output pairs. It

requires a fixed precision resistor to ground. 475ohm is the standard value for

100ohm differential impedance. Other impedances require different values. See

data sheet.

27

GNDA

PWR

Ground pin for the PLL core.

28

VDDA

PWR

3.3V power for the PLL core.

Note:

^ indicates internal 120K pull up

v indicates internal 120K pull down