SPV1020

Detailed description

Doc ID 17588 Rev 3

11/19

5.6

Overtemperature protection (OTP)

When the temperature sensed at silicon level reaches 150 °C, all low-side power switches

are immediately turned off. The device becomes operative again as soon as the silicon

temperature drops to 130 °C.

5.7

Shutdown

In shutdown mode, the SHUT command sent to the converter switches the converter off to

minimize power consumption. The synchronous rectifier intrinsic body diode causes a

parasitic path between the power supply input and output, that cannot be avoided in

shutdown.

5.8

Undervoltage lockout (UVLO)

When solar radiation is too low or the PV cells are shaded, the energy generated may be too

small to drive the converter. In this case, when the input voltage is lower than the UVLO

threshold, all circuitry is in the OFF state, avoiding undesired power consumption.

Hysteresis has been implemented to limit undesired switching of the internal reset circuits.

5.9

MPPT

In order to maximize the energy transferred from the PV cell string to the DC bus (connected

to the output of the converter) the converter embeds a logic running a

Perturb&Observe

operating voltage of the PV array is perturbed in a given direction and the power drawn from

the PV array increases, this means that the operating point has moved towards the MPP

and, therefore, the operating voltage must be further perturbed in the same direction.

Otherwise, if the power drawn from the PV array decreases, the operating point has moved

away from the MPP and, therefore, the direction of the operating voltage perturbation must

be reversed

5.10

SPI

The SPV1020 embeds a 4-pin compatible SPI interface. The SPI allows full duplex,

synchronous, serial communication between a host controller (the master) and the

SPV1020 peripheral device (the slave). The SPI master provides the synchronizing clock

and starts the communication. The idle state of the serial clock for the SPV1020 is high.

Data pins are driven on the falling edges of the serial clock and they are sampled on its

rising edges. These features correspond to a clock polarity set to 1 (typical host SPI control

bit CPOL=1) and to a clock phase set to 1 (typical host SPI control bit CPHA=1),

respectively. The bit order of each byte is MSB first.

When the master initiates a transmission, a data byte is shifted out through the MOSI pin to

the slave, while another data byte is shifted out through the MISO pin to the master. The

master controls the serial clock on the SCLK pin. The SS (active low) pin must be driven low

by the master during each transmission. The bit order of each byte is MSB first.

The SPV1020 register file is accessible by the host through the SPI bus. Therefore the host

can read the SPV1020 control parameter register data. Each data frame includes at least