Register description

LIS33DE

28/31

Doc ID 15596 Rev 1

7.10

FF_WU_THS (32h)

Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If

DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration

counter is decremented.

7.11

FF_WU_DURATION (33h)

Duration register for free-fall/wake-up interrupt. Duration step and maximum value depend

on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400 Hz, else step 10

msec, from 0 to 2.55 sec when ODR=100 Hz. The counter used to implement duration

function is blocked when LIR=1 in configuration register and the interrupt event is verified.

Table 32.

FF_WU_THS (32h) register

DCRM

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 33.

FF_WU_THS (32h) register description

DCRM

Resetting mode selection. Default value: 0

(0: counter reset; 1: counter decremented)

THS6, THS0

Free-fall / wake-up Threshold: default value: 000 0010

Table 34.

FF_WU_DURATION (33h) register

D7

D6

D5

D4

D3

D2

D1

D0

Table 35.

FF_WU_DURATION (33h) register description

D7-D0

Duration value. Default value: 0000 0000