SIP11205 datasheet(9/21 Pages) VISHAY

9 / 21 page

Document Number: 69233

S-81795-Rev. C, 04-Aug-08

www.vishay.com

Vishay Siliconix

SiP11205

And the duty cycle on DL or DH will then be approximately

half of DTOTAL. Please note that due to oscillator comparator

overshoot the exact duty cycle calculated using above

formula may be slightly different. To better understand the

PWM operation during start up refer to "Timing Diagram and

Soft Start Duty Cycle Control" graph, for PWM operation

after start up see "Feed-Forward Function Diagram".

For each specific application the RDB1/RDB2 ratio must be

chosen to provide maximum duty cycle with appropriate

dead time at minimum supply voltage. The voltage at RDB pin

that corresponds to maximum duty cycle at minimum input

voltage can be determined by applying a precise voltage

source on this pin for the dead time required. The SiP11205

has a stable 3.3 V reference with 3 % temperature accuracy,

so a typical 3 % duty variation and 1 % DL/DH matching can

be achieved. There will be 0.75 % duty reduction for each 1

V increase in the VIN supply range. For better system

efficiency it is recommended that the input voltage range be

limited to 42 V to 55 V.

Soft Start

The soft start circuit plays an important role in protecting the

controller. At startup it prevents high in-rush current. During

a normal start-up sequence (VCS < VMOC. VCS is the voltage

at CS pin), or following any event that would cause a

hiccup-and-soft-start sequence, CSS will be charged from

about 0 V to a final voltage of 2 VBE + VINDET/2 at a 20 µA

rate. As the voltage on the CSS rises towards the final

voltage, the maximum permitted DL and DH duty cycles will

increase from 0 % to a maximum defined by the RDB resistor

divider.

When a mild fault condition is detected (VCS = VMOC), CSS

goes into a hiccup mode until fault condition is removed. The

hiccup is activated when CSS discharges to 0.85 VSS at

20 µA and subsequently at 0.4 µA until the fault condition is

removed. Refer to "Fault Conditions and Responses" for

details.

Fault Conditions and Responses

The faults that can cause a hiccup-and-retry cycle are

moderate over-current (MOC), severe over-current (SOC),

chip level UVLO, system level UVLO, and over temperature

protection (OTP).

Prior to detailing the various fault conditions and responses,

some definitions are given:

1. A complete switching period, T, consists of two oscillator

cycles TDL and TDH.

2. TDL (TDH) is the oscillator cycle during which the DL (DH)

output is in the high state.

3. T is defined as starting at the beginning of TDL, and

terminating at the end of TDH.

Response to MOC Faults (VMOC < VCS < VSOC):

Once SiP11205 has completed a normal soft-start cycle, VSS

will be clamped at the final voltage, allowing the maximum

possible duty cycle on DL and DH.

If an MOC fault occurs following the start-up (due to a

condition such as an excessive load on the converter’s

output), SiP11205 will respond by gradually reducing the

available maximum duty cycle of its DL and DH outputs each

to be equal to approximately 42 % of their possible 47 %

maximum values. This is before any effects of deadtime

introduced by RDB are added in. This reduction in available

maximum duty cycle is achieved by reducing the voltage on

the SS pin to 4 V, as follows:

1. If VMOC < VCS < VSOC at any time during TDL, a current

of 20 µA will be drawn out of the SS pin until the

beginning of the next TDL.

2. If the voltage on the SS pin remains above the value that

would allow an available maximum DL and DH duty cycle

of 42 %, SiP11205 will continue operating.

3. If the voltage on the SS pin goes below the value that

would allow an available maximum DL and DH duty cycle

of 42 %, a hiccup interval is started, during which both DL

and DH are held in their low states.

4. The SS pin is discharged towards 0 V by a 400 nA sink

current.

5. The hiccup interval is terminated when the SS pin is

discharged to 0.25 V.

After the above actions have been taken switching on the DL

and DH outputs will then resume with a normal soft-start

cycle.

Response to MOC faults is enabled after the successful

completion of any normal soft-start cycle.

Response to SOC Faults (VCS > VSOC):

This is an immediate, single-cycle response over current

shutdown, followed by a hiccup delay and a normal soft-start

cycle. Since this is a gross fault protection mechanism, its

triggering mechanism is asynchronous to the timing of TDL

and TDH.

1. If VCS > VSOC, a hiccup interval is started, during which

both DL and DH are held in their low states.

2. The SS pin is discharged towards 0 V by a 400 nA sink

current.

3. The hiccup interval is terminated when the SS pin is

discharged to 0.25 V.

4. Switching on the DL and DH outputs will then resume

with a normal soft-start cycle.

Severe over current response is enabled at all times,

including the initial ramp-up period of the soft-start pin. This

allows SiP11205 to provide rapid fault protection for the

converter’s power train.

SIP11205 датащи(PDF) 9 Page - Vishay Siliconix

SIP11205 датащи(HTML) 9 Page - Vishay Siliconix

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

датащи скачать

ссылки URL