SIC403 datasheet(17/25 Pages) VISHAY

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Vishay Siliconix

SiC403

Document Number: 66550

S11-1638-Rev. B, 15-Aug-11

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Another way to eliminate doubling-pulsing is to add a small

(~ 10 pF) capacitor across the upper feedback resistor, as

shown in figure 11. This capacitor should be left unpopulated

until it can be confirmed that double-pulsing exists. Adding

the CTOP capacitor will couple more ripple into FB to help

eliminate the problem. An optional connection on the PCB

should be available for this capacitor.

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking

stability is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and ringing.

Ringing for more than one cycle after the initial step is an

indication that the ESR should be increased.

One simple way to solve this problem is to add trace

resistance in the high current output path. A side effect of

adding trace resistance is output decreased load regulation.

ESR Requirements

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide10 mVp-p

at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insufficient

ESR. The on-time control regulates the valley of the output

ripple voltage. This ripple voltage is the sum of the two

voltages. One is the ripple generated by the ESR, the other

is the ripple due to capacitive charging and discharging

during the switching cycle. For most applications the

minimum ESR ripple voltage is dominated by the output

capacitors, typically SP or POSCAP devices. For stability the

ESR zero of the output capacitor should be lower than

approximately one-third the switching frequency. The

formula for minimum ESR is shown by the following

equation.

For applications using ceramic output capacitors, the ESR is

normally too small to meet the above ESR criteria. In these

applications it is necessary to add a small virtual ESR

network composed of two capacitors and one resistor, as

shown in figure 12. This network creates a ramp voltage

across CL, analogous to the ramp voltage generated across

the ESR of a standard capacitor. This ramp is then

capacitive-coupled into the FB pin via capacitor CC.

Dropout Performance

The output voltage adjusts range for continuous-conduction

operation is limited by the fixed 250 ns (typical) minimum

off-time of the one-shot. When working with low input

voltages, the duty-factor limit must be calculated using

worst-case values for on and off times. The duty-factor

limitation is shown by the next equation.

The inductor resistance and MOSFET on-state voltage drops

must be included when performing worst-case dropout

duty-factor calculations.

System DC Accuracy (VOUT Controller)

Three factors affect VOUT accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line and

load, and the external resistor tolerance. The error

comparator off set is trimmed so that under static conditions

it trips when the feedback pin is 750 mV, 1 %.

The on-time pulse from the SiC403 in the design example is

calculated to give a pseudo-fixed frequency of 250 kHz.

Some frequency variation with line and load is expected.

This variation changes the output ripple voltage. Because

constant on-time converters regulate to the valley of the

output ripple, ½ of the output ripple appears as a DC

regulation error. For example, if the output ripple is 50 mV

with VIN = 6 V, then the measured DC output will be 25 mV

above the comparator trip point. If the ripple increases to

80 mV with VIN = 25 V, then the measured DC output will be

40 mV above the comparator trip. The best way to minimize

this effect is to minimize the output ripple.

Figure 11 - Capacitor Coupling to FB Pin

VOUT

To FB pin

CTOP

ESRMIN =

2 x

π x COUT x fSW

Figure 12 - Virtual ESR Ramp Current

COUT

High-

side

Low-

side

DUTY =

TON(MIN)

TON(MIN) x TOFF(MAX)

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