HT82V46 datasheet(21/27 Pages) HOLTEK

21 / 27 page

Rev. 1.10

November 24, 2011

HT82V46

Name

POR.

Description

Setup

LNBYLN

Selects line by line operation. Line by line operation is intended for use

with systems which operate one line at a time but with up to three color

shared on the one output.

ACYC

If LNBYLN=0 then ACYC bit no effect.

ACYC bit determines CDS1 pin and offset/gain register controls

0= CDS1 pin is for Reference Sampling or Reset Level Clamp

control. And INTM[1:0] bits are for gain/offset multiplexers control.

1= Auto-cycling enabled by pulsing CDS1 pin and input signal

switched to next gain/offset register sequentially. And sequence is

Red -> Green -> Blue -> Red etc. At this mode, it must set

CDS=0 and use CLPCTL bit instead CDS1 pin to control RLC.

3:2

INTM[1:0

When LNBYLN=0 or ACYC=1 this bit has no effect.

When LNBYLN=1 and ACYC=0.

Controls the offset/gain mux selector.

00= Red offset/gain registers applied to input channel.

01= Green offset/gain registers applied to input channel.

10= Blue offset/gain registers applied to input channel.

11= Reserved.

7:4

Reserved

0000

Setup

REDPD

When set powers down red S/H, PGA

GRNPD

When set powers down green S/H, PGA

BLUPD

When set powers down blue S/H, PGA

ADCPD

When set powers down ADC, allows reduced power consumption

without powering down the references which have a long time constant

when switching on/off due to the external decoupling capacitors.

CDACPD

When set powers down 4-bit RLCDAC, setting the output to a high

impedance state and allowing an external reference to be driven in on

the VRLC/VBIAS pin.

REFPD

When set disables REFT, REFB buffers to allow external references to

be used.

CMLPD

When set disable CML buffer to allow an externa reference to be used.

Reserved

Must be set to 0

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