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FM

31

64

FM3130 Integrated RTC/Alarm with 64Kb FRAM

Rev. 3.2

Sept. 2011

Page 19 of 22

AC Test Conditions

Equivalent AC Test Load Circuit

Input Pulse Levels

Input rise and fall times

10 ns

Input and output timing levels

Diagram Notes

All start and stop timing parameters apply to both read and write

cycles. Clock specifications are identical for read and write cycles.

Write timing parameters apply to slave address, word address, and

write data bits. Functional relationships are illustrated in the relevant

data sheet sections. These diagrams illustrate the timing parameters

only.

Read Bus Timing

t

SU:STA

Start

t

R

`

t

F

Stop Start

t

BUF

t

HIGH

t

LOW

t

SP

t

SP

Acknowledge

t

HD:DAT

t

SU:DAT

t

AA

t

DH

SCL

SDA

Write Bus Timing

t

SU:STO

Start

Stop Start

Acknowledge

t

AA

t

HD:DAT

t

HD:STA

t

SU:DAT

SCL

SDA

Power Cycle Timing

VDD

2.7V

Can user

access device?

t

RPU

yes

no

yes

3.6V

Output

1100



100 pF