GS7025 PRO-LINX™ Serial Digital Receiver

Data Sheet

13813 - 7

October 2009

13 of 23

NOTE: For maximum cable length performance the OEM_TEST block should be

disabled.

3.2 Reclocker

The reclocker receives a differential serial data stream from the internal multiplexer. It

locks an internal clock to the incoming data. It outputs the differential PECL retimed

data signal on SDO/SDO. It outputs the recovered clock on SCO/SCO. The timing

between the output and clock signals is shown in Figure 3-2.

Figure 3-2: Output and Clock Signal Timing

The reclocker contains three main functional blocks: the Phase Locked Loop, Frequency

Acquisition, and Logic Circuit.

3.2.1 Phase Locked Loop (PLL)

The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A

simplified block diagram of the PLL is shown in Figure 3-3 below. The main components

are the VCO, the phase detector, the charge pump, and the loop filter.

Figure 3-3: Simplified Block Diagram of the PLL

SDO

SCO

50%

DDI/DDI

LF+

LFS

LF-

VCO

2

PHASE

DETECTOR

INTERNAL

PLL CLOCK

CHARGE

PUMP

LOOP

FILTER