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L3G4200D датащи(PDF) 29 Page - STMicroelectronics |
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L3G4200D датащи(HTML) 29 Page - STMicroelectronics |
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29 / 42 page ![]() L3G4200D Register description Doc ID 17116 Rev 3 29/42 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 WHO_AM_I (0Fh) Device identification register. 7.2 CTRL_REG1 (20h) DR<1:0> is used to set ODR selection. BW <1:0> is used to set Bandwidth selection. In the following table are reported all frequency resulting in combination of DR / BW bits. Table 19. WHO_AM_I register 1 101 00 11 Table 20. CTRL_REG1 register DR1 DR0 BW1 BW0 PD Zen Yen Xen Table 21. CTRL_REG1 description DR1-DR0 Output Data Rate selection. Refer to Table 22 BW1-BW0 Bandwidth selection. Refer to Table 22 PD Power down mode enable. Default value: 0 (0: power down mode, 1: normal mode or sleep mode) Zen Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Yen Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) Xen X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled) Table 22. DR and BW configuration setting DR <1:0> BW <1:0> ODR [Hz] Cut-Off 00 00 100 12.5 00 01 100 25 00 10 100 25 00 11 100 25 |
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