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LIS3DH датащи(PDF) 36 Page - STMicroelectronics |
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LIS3DH датащи(HTML) 36 Page - STMicroelectronics |
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36 / 42 page ![]() Registers description LIS3DH 36/42 Doc ID 17530 Rev 1 Interrupt 1 source register. Read only register. Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen. 8.23 INT1_THS (32h) 8.24 INT1_DURATION (33h) D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 8.25 CLICK_CFG (38h) YL Y low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred) XH X high. Default value: 0 (0: no interrupt, 1: X High event has occurred) XL X low. Default value: 0 (0: no interrupt, 1: X Low event has occurred) Table 50. INT1_SRC description Table 51. INT1_THS register 0 THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 52. INT1_THS description THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000 Table 53. INT1_DURATION register 0 D6 D5D4D3 D2D1 D0 Table 54. INT1_DURATION description D6 - D0 Duration value. Default value: 000 0000 Table 55. CLICK_CFG register -- -- ZD ZS YD YS XD XS |
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