SM5K3 datasheet(15/28 Pages) SHARP

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SM5K3/SM5K4/SM5K5

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• Blocks stopped during standby mode

In the halt mode

The system clock generating circuit stops during

the halt mode, deactivating all the blocks driven by

the system clock. The main clock and dividers

remain active. This means that timers can be used

while in the halt mode. Both internal and external

clocks can be used as the count clock.

In the stop mode

The main clock and system clock stop upon

entering the stop mode. Therefore, only timers

using the external clock remain active.

• Counters that the system retains during

standby mode

The contents that will be retained in the halt mode

will also be retained in the stop mode. These items

are shown in Table 3.

Operation mode

Standby mode

HALT mode

Run HALT command

HALT mode

release event

Normal

operation

Run STOP command

STOP mode

release event

STOP mode

Fig. 8

Operation Shift of Program

Table 3

System Contents Secured During Standby Mode

FLAG

OUTPUT LATCH REGISTER/MODE REGISTER

OTHER

IFA flag

IFB flag

IFT flag

IME flag

flag

A register

X register

BM, BL register

P0, P2, R3, P5

R8, R9, RA, RB

RC, RE, RF

RAM

• Releasing events of standby mode (6-type)

RELEASING EVENT

FLAG

INT/EXT

MASKABLE / NONMASKABLE

PRIORITY

Reset input

–

External

Nonmaskable

–

Low level input on P10 pin

IFA

External

Maskable

Low level input on P11 pin

IFB

External

Maskable

Low level input on P12 pin

–

External

Nonmaskable

–

Low level input on P13 pin

–

External

Nonmaskable

–

Timer overflow

IFT

Internal

Maskable

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