Serial Interface

The MAX7301 communicates through an SPI-compati-

ble 4-wire serial interface. The interface has three

inputs, Clock (SCLK), Chip Select (

CS), and Data In

(DIN), and one output, Data Out (DOUT).

CS must be

low to clock data into or out of the device, and DIN

must be stable when sampled on the rising edge of

SCLK. DOUT provides a copy of the bit that was input

15.5 clocks earlier, or upon a query it outputs internal

register data, and is stable on the rising edge of SCLK.

Note that the SPI protocol expects DOUT to be high

impedance when the MAX7301 is not being

accessed; DOUT on the MAX7301 is never high

impedance. See www.maxim-ic.com/an 1879 for

ways to convert DOUT to tri-state, if required.

SCLK and DIN may be used to transmit data to other

peripherals, so the MAX7301 ignores all activity on

SCLK and DIN except between the fall and subsequent

rise of

CS.

Control and Operation Using the

4-Wire Interface

Controlling the MAX7301 requires sending a 16-bit

word. The first byte, D15 through D8, is the command

address (Table 3), and the second byte, D7 through

D0, is the data byte (Table 4 through Table 8).

Connecting Multiple MAX7301s

to the 4-Wire Bus

Multiple MAX7301s may be daisy-chained by connect-

ing the DOUT of one device to the DIN of the next, and

driving SCLK and

CS lines in parallel (Figure 3). Data at

DIN propagates through the internal shift registers and

appears at DOUT 15.5 clock cycles later, clocked out

on the falling edge of SCLK. When sending commands

to multiple MAX7301s, all devices are accessed at the

where n is the number of MAX7301s connected togeth-

er. To update just one device in a daisy-chain, the user

can send the No-Op command (0x00) to the others.

Writing Device Registers

The MAX7301 contains a 16-bit shift register into which

DIN data are clocked on the rising edge of SCLK, when

CS is low. When CS is high, transitions on SCLK have

no effect. When

CS goes high, the 16 bits in the Shift

register are parallel loaded into a 16-bit latch. The 16

bits in the latch are then decoded and executed.

4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and

28-Port I/O Expander

6

_______________________________________________________________________________________

Table 1. Port Configuration Map

REGISTER DATA

REGISTER

ADDRESS

CODE (HEX)

D7

D6

D5

D4

D3

D2

D1

D0

Port Configuration for P7, P6, P5, P4

0x09

P7

P6

P5

P4

Port Configuration for P11, P10, P9, P8

0x0A

P11

P10

P9

P8

Port Configuration for P15, P14, P13, P12

0x0B

P15

P14

P13

P12

Port Configuration for P19, P18, P17, P16

0x0C

P19

P18

P17

P16

Port Configuration for P23, P22, P21, P20

0x0D

P23

P22

P21

P20

Port Configuration for P27, P26, P25, P24

0x0E

P27

P26

P25

P24

Port Configuration for P31, P30, P29, P28

0x0F

P31

P30

P29

P28

Table 2. Port Configuration Matrix

PORT

CONFIGURATION

BIT PAIR

MODE

FUNCTION

PORT

REGISTER

(0x20–0x5F)

(0xA0–0xDF)

PIN BEHAVIOR

ADDRESS

CODE (HEX)

UPPER

LOWER

DO NOT USE THIS SETTING

0x09 to 0x0F

00

Register bit = 0

Active-low logic output

Output

GPIO Output

Register bit = 1

Active-high logic output

0x09 to 0x0F

01

Input

GPIO Input

Without Pullup

Schmitt logic input

0x09 to 0x0F

10

Input

GPIO Input with Pullup

Register bit =

input logic level

Schmitt logic input with pullup

0x09 to 0x0F

11