SPEC No.

LCY-12T09302A

MODEL No.

LS013B4DN01

PAGE

12

6-4）Power consumption (Average)

Table6-4

Ta＝25℃

Item

Symbol

MIN

TYP

MAX

unit

Remark

Condition1

15

uW

[Remark6-6]

Condition2

30

uW

[Remark6-6]

＊

Condition1

Display mode (No display data update)

Common AC Driving with VDD=5V, VDDA=5V, fSCLK=1MHz, fSCS=１Hz, Display pattern: Vertical stripe display

＊

Condition 2

Data Renew mode (With display data update: 1Hz)

Common AC Driving with VDD=5V, VDDA=5V, fSCLK=1MHz, fSCS=１Hz, Display pattern: Vertical stripe display

[Remark6-6] This is the average power in normal condition, not the peak power for COM driving.

Allow margin in power supply. Use of capacitor is recommended for VDD+VDDA.

(If VDD and VDDA are separate, use of capacitor on each is recommended.)

6-5）Input Signal Timing Chart

6-5-1 Data Renew Mode (1 line)

Renews data on one specified line. (M0=”H”, M2=”L”)

Renews data on one specified line. (M0=”H”, M2=”L”)

SCS

SI

M0 M1 M2 DMYDMYDMYDMYDMY AG0 AG1 AG2 AG3 AG4 AG5 AG6 DMY D1 D2 D3 D4

D93 D94 D95 D96

DUMMY DATA(don't care)

SCLK

・

M0：Mode flag: If M0 is "H". -> Data refresh mode "Pixel data will be updated" . If M0 is "L" -> Display mode "Pixel data is held.

・

M1：LC polarity inversion flag: If M1is "H" then VCOM="H" is output. If M1 is "L" then VCOM="L" is output. In addition, if EXTMODE is set as "H", M1 set value doesn't matter.

・

M2：All flags are cleared. If M2 is "L" then all flags are cleared.

When all clear are needed, refer to "all clear timing chart"

・

D1 - D96：Display data: If D* is "L" then Black display can be appeared, if D* is "H" then White display can be appeared

・

DUMMY DATA： Dummy data. Don't care but "L" is recommended

tsSI

thSI

tsSCS

Data writing period

(96ck)

Data transfer period

(16ck)

Mode selection period

(3ck+5ckDMY)

twSCLKH

twSCLKL

twSCSH

Gate line address period

(7ck+1ckDMY)

thSCS

twSCSL

※

In terms of Data writing period

Data has been stored in 1st latch block of Binary driver on

Panel.

※

In term of Data transfer period

The data which has been stored in 1st latch block is

transferred to pixel memory.

※

Refer to 6-6) Input Signal and Display for gate line address setting.

※

M1: Frame inversion flag is enabled when EXTMODE=”L”.

※

When SCS becomes L, M0 and M2 are cleared.

※

In renew mode (When M2=”H”) do “All Clear”, and set P1 through P96 as L.