ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

CIRCUIT INFORMATION

WATCHDOG

TRANSITION

DETECTOR

WATCHDOG

INPUT (WDI)

POWER-FAIL

INPUT (PFI)

POWER-FAIL

WATCHDOG

OUTPUT (WDO)

RESET,

(P = RESET)

Rev. C | Page 10 of 16

OUTPUT (PFO)

*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)

RESET AND

WATCHDOG

TIMEBASE

RESET

GENERATOR

MR

70μA

WATCHDOG

TIMER

1.25V

ADM706P/ADM706R/

ADM706S/ADM706T

Figure 13. ADM706 Functional Block Diagram

1.25V

POWER-FAIL

INPUT (PFI)

RESET

* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)

RESET

GENERATOR

MR

70μA

RESET

POWER-FAIL

OUTPUT (PFO)

ADM708R/ADM708S/

ADM708T

Figure 14. ADM708 Functional Block Diagram

POWER-FAIL RESET

The reset output provides a reset (RESET or RESET) output

the reset threshold. The actual reset threshold voltage is dependent

on whether a P, R, S, or T suffix device is used. An internal timer

rises above the threshold. This is intended as a power-on reset

signal for the microprocessor. It allows time for both the power

supply and the microprocessor to stabilize after power-up. If a

power supply brownout or interruption occurs, the reset line is

similarly activated and remains active for 200 ms after the supply

recovers. If another interruption occurs during an active reset

period, the reset timeout period continues for an additional 200 ms.

as 1 V. This ensures that the microprocessor is held in a stable

shutdown condition as the power supply starts up.

The ADM706P provides an active high RESET signal; the

ADM706R/ADM706S/ADM706T provide an active low RESET

signal; and the ADM708R/ADM706S/ADM706T provide both

RESET and RESET.

MANUAL RESET

The MR input allows other reset sources, such as a manual reset

switch, to generate a processor reset. The input is effectively

debounced by the timeout period (200 ms typical). The MR

input is TTL-/CMOS-compatible; it can also be driven by any

logic reset output. If unused, the MR input can be tied high or

left floating.

MR EXTERNALLY

DRIVEN LOW

RESET

MR

WDO

NOTES

RESET = COMPLEMENT OF RESET

Figure 15. RESET, MR, and WDO Timing

WATCHDOG TIMER (ADM706x)

The watchdog timer circuit is used to monitor the activity of the

microprocessor to check that it is not stalled in an indefinite loop.

An output line on the processor is used to toggle the watchdog

input (WDI) line. If this line is not toggled within the timeout

period (1.6 seconds), the watchdog output (WDO) is driven low.

The WDO output is connected to a nonmaskable interrupt (NMI)

on the processor. Therefore, if the watchdog timer times out, an

interrupt is generated. The interrupt service routine is used to

rectify the problem.

The watchdog timer is cleared either by a high-to-low or by a

low-to-high transition on WDI. Pulses as narrow as 50 ns are

detected. The timer is also cleared by RESET/RESET going

active. Therefore, the watchdog timeout period begins after

reset goes inactive.

whether or not the watchdog timer has timed out. Normally,

this generates an interrupt, but it is overridden by RESET/RESET

going active.

WDI

WDO

RESET

RESET EXTERNALLY

TRIGGERED BY MR

Figure 16. Watchdog Timing