ACT8798 datasheet(24/34 Pages) ACTIVE-SEMI

24 / 34 page

STEP-DOWN DC/DC CONVERTERS

ACT8798

Rev 1, 16-Nov-09

Innovative PowerTM

- 24 -

www.active-semi.com

ActivePMUTM is a trademark of Active-Semi.

I2CTM is a trademark of Philips Electronics.

Active-Semi

Input Capacitor Selection

The input capacitor reduces peak currents and

noise induced upon the voltage source. A 2.2µF

ceramic capacitor for each of REG1, REG2, and

REG3 is recommended for most applications.

Output Capacitor Selection

For most applications, 10µF ceramic output

capacitors are recommended for REG1, REG2, and

REG3.

Although

the

these

regulators

were

designed to take advantage of the benefits of

ceramic capacitors, namely small size and very-low

ESR, low-ESR tantalum capacitors can provide

acceptable results as well.

Inductor Selection

REG1, REG2, and REG3 utilize current-mode

control and a proprietary internal compensation

scheme

simultaneously

simplify

external

component

selection

and

optimize

transient

performance over their full operating range. These

devices were optimized for operation with 3.3µH

inductors, although inductors in the 2.2µH to 4.7µH

range can be used. Choose an inductor with a low

DC-resistance, and avoid inductor saturation by

choosing inductors with DC ratings that exceed the

maximum output current of the application by at

least 30%.

PCB Layout Considerations

High switching frequencies and large peak currents

make PC board layout an important part of step-

down DC/DC converter design. A good design

minimizes excessive EMI on the feedback paths

and voltage gradients in the ground plane, both of

which can result in instability or regulation errors.

Step-down DC/DCs exhibit discontinuous input

current, so the input capacitors should be placed as

close as possible to the IC, and avoiding the use of

via if possible. The inductor, input filter capacitor,

and output filter capacitor should be connected as

close together as possible, with short, direct, and

wide traces. The ground nodes for each regulator's

power loop should be connected at a single point in

a star-ground configuration, and this point should

be connected to the backside ground plane with

multiple via. The output node for each regulator

should be connected to its corresponding OUTx pin

through the shortest possible route, while keeping

sufficient distance from switching nodes to prevent

noise injection. Finally, the exposed pad should be

directly connected to the backside ground plane

using multiple via to achieve low electrical and

thermal resistance.

FUNCTIONAL DESCRIPTION (CONT’D)

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