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LH28F016LL датащи(PDF) 3 Page - Sharp Corporation |
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LH28F016LL датащи(HTML) 3 Page - Sharp Corporation |
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3 / 29 page ![]() 16M (1M × 16, 2M × 8) Flash Memory LH28F016LL 3 PIN DESCRIPTION SYMBOL TYPE NAME AND FUNCTION A 0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE is high). A 1 - A15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64K block. A 6 - A15 selects 1 of 1024 rows, and A 1 - A5 selects 16 of 512 columns. These addresses are latched during Data Writes. A 16 - A20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during Data Writes, Erase and Lock-Block operations. DQ 0 - DQ7 INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled. DQ 8 - DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS : Inputs data during x16 Data-Write operations. Outputs array, buffer or identifier data in the appropriate Read mode; not used for Status register reads. Floated when the chip is de-selected or the outputs are disabled. CE » 0, CE »1 INPUT CHIP ENABLE INPUTS : Activate the device’s control logic, input buffers, decoders and sense amplifiers. With either CE » 0 or CE »1 high, the device is de-selected and power consumption reduces to Standby levels upon completion of any current Data-Write or Erase operations. Both CE » 0, CE »1 must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE » 0 or CE »1. The first rising edge of CE»0 or CE »1 disables the device. RP » INPUT RESET/POWER-DOWN: RP » low places the device in a Deep Power-Down state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of 5 ns is required to allow these circuits to power-up for Read mode, and another 395 ns is required to enter Program or Erase mode. When RP » goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status registers return to ready (with all status flags cleared). OE » INPUT OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE » is high. NOTE: CE » X overrides OE », and OE » overrides WE. WE INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE is active low, and latches both address and data (command or array) on its rising edge. RY »/BY » OPEN DRAIN OUTPUT READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY »/BY » high indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or Erase is Suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE » or CE » 0, CE »1 are high), except if a RY»/BY » Pin Disable command is issued. |
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