SC1401 datasheet(12/17 Pages) SEMTECH

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SC1401

652 MITCHELL ROAD

NEWBURY PARK CA 91320

HIGH PERFORMANCE SYNCHRONOUS BUCK

CONTROLLER WITH LDO FOR PORTABLE

POWER

November 21, 2000

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

Detailed Description

The SC1401 is a high performance, high efficiency,

PWM synchronous buck controller, designed to

power the latest generation microprocessors in

battery operated systems. Two high-current gate

drive outputs are supplied to control both MOSFETs

in the synchronous rectified buck converter. This

power supply can be programmed to operate at

either fixed (1.25V) or adjustable output voltages.

The power save feature enables high efficiency over

a wide range of load current. The control and fault

monitoring circuitry associated with the PWM

controller includes digital softstart, turn-on

sequencing, frequency compensation, power save,

overcurrent and over and under voltage fault

protection. An LDO NMOS linear regulator is also

generated by the SC1401. A block diagram of the

SC1401 is shown in Figure 1.

PWM Control Block

The SC1401 employs peak-current-mode control with

slope compensation to provide fast output response

to load and line transients. The PWM control block

consists of an analog PWM modulator followed by

PWM logic control. The analog modulator combines

the current output, slope compensation signal and

error voltage to generate a PWM pulse train. The

PWM logic uses the pulse train from the modulator

and other control signals to generate the output

states for the high and low side gate driver outputs.

A block diagram of the PWM control block is shown

in Figure 2.

An error amplifier generates the difference signal

between the reference voltage and the feedback

voltage to generate the control voltage for the peak

current mode comparator. A nominal gain of 8 is

used in the error amplifier to further increase the

system loop-gain and reduce the load regulation

error typically seen with low loop-gain current mode

controllers. The increased gain in the voltage loop is

compensated by pole-zero-pole response of the

voltage error amplifier. The current feedback signal

is summed with the slope compensation signal and

compared to the control voltage by the PWM

comparator.

When the power supply is operating in continuous

conduction mode with current > 25% of its peak

value, the high side MOSFET is turned on at the

beginning of each switching cycle. The high-side

MOSFET is turned off when the desired duty cycle is

reached. Active shoot-through protection delays the

turn-on of the low-side power device until the

PHASE node drops below 1.25V. The low-side

devices remains on until the beginning of the next

switching cycle. Again, active shoot-through

protection ensures that the gate to the low-side

power device is low before the high-side device is

turned on.

When PSAVE is enabled (low) and the output

current drops below 25% of its peak level, the PWM

logic will automatically enter PSAVE mode to

improve efficiency. When the controller enters

power save, it increases the regulation point by

0.8%, typically issuing one more high side pulse as

the converter enters PSAVE. The PWM control

then disables switching cycles until the FB falls

below the reference. At light loads the effective

switching frequency will drop dramatically and

efficiency will increase because of the reduced gate

charge current required to switch the power stage.

Boosting the regulation point when entering PSAVE

gives the output improved dynamic regulation

because the output voltage is not allowed to droop

below the nominal regulation point. Load current

steps, that cause the converter to come out of

PSAVE, will not cause as large a negative dip in the

output voltage.

The PSAVE threshold is a function of the load and

peak-to-peak inductor current. It can be calculated

by the following equations:

!IL = peak-to-peak inductor current

IO = Load Current

VIN = Input Voltage

VO = Output Voltage

D = Duty Cycle

f = Frequency

L = Inductance

THPSAVE

∆I

•













()

∆I

•

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