Application details

L6727

18/34

Doc ID 12933 Rev 4

same high-current trace on more than one PCB layer will reduce the parasitic resistance

associated to that connection.

inductance and resistance associated to the copper trace, also adding extra decoupling

capacitors along the way to the load when this results in being far from the bulk capacitors

bank.

Figure 8.

Power connections (heavy lines)

Gate traces and phase trace must be sized according to the driver RMS current delivered to

the power MOSFET. The device robustness allows managing applications with the power

section far from the controller without losing performances. Anyway, when possible, it is

recommended to minimize the distance between controller and power section. See Figure 9

for drivers current paths.

Small signal components and connections to critical nodes of the application, as well as

bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC

and Bootstrap capacitor) and loop compensation components as close to the device as

leakage current paths on COMP / OC pin, since the internal current source is only 60

μA.

Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big

negative spikes on the phase pin. This spike must be limited within the absolute maximum

ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase

resistor in series to PHASE pin), as well as the positive spike, but has an additional

consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can

cause, in the worst case condition of maximum input voltage and during particular

transients, that boot-to-phase voltage overcomes the absolute maximum ratings also

causing device failures. It is then suggested in this cases to limit this extra-charge by adding

Figure 9.

Drivers turn-on and turn-off paths

L

UGATE

PHASE

LGATE

GND

LOAD

L6727

VCC

LS DRIVER

LS MOSFET

GND

LGATE

BOOT

HS DRIVER

HS MOSFET

PHASE

UGATE