Philips Semiconductors

PCF85103C-2

256

Product data

Rev. 04 — 22 October 2004

11 of 20

9397 750 14218

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

[1]

The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by

a transmitter.

Table 8:

Symbol

Parameter

Conditions

Min

Max

Unit

clock frequency

0

100

kHz

bus free time between a STOP and

START condition

4.7

−µs

START condition hold time after

which first clock pulse is generated

4.0

−µs

LOW level clock period

4.7

−µs

HIGH level clock period

4.0

−µs

set-up time for START condition

repeated start

4.7

−µs

data hold time

for bus compatible masters

5

−µs

for bus devices

[1]

0

−

ns

data set-up time

250

−

ns

SDA and SCL rise time

−

1

µs

SDA and SCL fall time

−

300

ns

set-up time for STOP condition

4.0

−µs

P = STOP condition; S = START condition.

Fig 9.

MBA705

t BUF

HD;STA

t

SCL

SDA

P

S

t LOW

t r

HD;DAT

t

SU;DAT

t

t f

t HIGH

S

HD;STA

t

SU;STA

t

SU;STO

t

P