Philips Semiconductors

Product data sheet

PCA9564

2006 Sep 01

3

PIN CONFIGURATION — DIP, SO, TSSOP

1

2

3

4

5

6

7

8

9

11

12

13

14

15

16

17

18

19

20

D0

D1

D2

D3

D4

D5

D6

D7

DNU

SDA

SCL

RESET

INT

A1

A0

RD

CE

WR

10

SW02260

PIN CONFIGURATION — HVQFN

15

14

13

12

11

1

2

3

4

5

SW02261

TOP VIEW

D3

D4

D5

D6

D7

INT

RESET

A0

A1

SCL

PIN DESCRIPTION

PIN NUMBER

PIN

DIP, SO, TSSOP

HVQFN

SYMBOL

PIN

TYPE

NAME AND FUNCTION

1, 2, 3, 4,

5, 6, 7, 8

1, 2, 3, 4, 5,

18, 19, 20

D0–D7

I/O

Data Bus: Bi-directional 3-State data bus used to transfer commands, data and

status between the controller and the CPU. D0 is the least significant bit.

9

6

DNU

Do not use: must be left floating (pulled LOW internally)

10

Pwr

Ground

11

8

WR

I

Write Strobe: When LOW and CE is also LOW, the contents of the data bus is

loaded into the addressed register. The transfer occurs on the rising edge of the

signal.

12

9

RD

I

Read Strobe: When LOW and CE is also LOW, causes the contents of the

addressed register to be presented on the data bus. The read cycle begins on the

falling edge of RD.

13

10

CE

I

Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU

and the controller are enabled on D0–D7 as controlled by the WR, RD and A0–A1

inputs. When HIGH, places the D0–D7 lines in the 3-State condition.

14, 15

11, 12

A0, A1

I

Address Inputs: Selects the controller internal registers and ports for read/write

operations.

16

13

INT

O

Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up

device.

17

14

RESET

I

18

15

SCL

I/O

19

16

SDA

I/O

20

17

Pwr

Power Supply: 2.3 to 3.6 V

NOTES:

proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board

using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in

the PCB in the thermal pad region.