ATMEGA48P_10 datasheet(6/420 Pages) ATMEL

6 / 420 page

8025L–AVR–7/10

ATmega48P/88P/168P

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega48P/88P/168P provides the following features: 4K/8K/16K bytes of In-System Pro-

grammable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM,

512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers,

three flexible Timer/Counters with compare modes, internal and external interrupts, a serial pro-

grammable USART, a byte-oriented, 2-wire Serial Interface, an SPI serial port, a 6-channel 10-

bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with

internal Oscillator, and five software selectable power saving modes. The Idle mode stops the

CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and

interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.

In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the

CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise dur-

ing ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest

of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega48P/88P/168P is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embedded control applications.

The ATmega48P/88P/168P AVR is supported with a full suite of program and system develop-

ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit

Emulators, and Evaluation kits.

2.2

Comparison Between ATmega48P, ATmega88P and ATmega168P

The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader sup-

port, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector

sizes for the three devices.

ATmega88P and ATmega168P support a real Read-While-Write Self-Programming mechanism.

There is a separate Boot Loader Section, and the SPM instruction can only execute from there.

Table 2-1.

Memory Size Summary

Device

Flash

EEPROM

RAM

Interrupt Vector Size

ATmega48P

4K Bytes

256 Bytes

512 Bytes

1 instruction word/vector

ATmega88P

8K Bytes

512 Bytes

1K Bytes

1 instruction word/vector

ATmega168P

16K Bytes

512 Bytes

1K Bytes

2 instruction words/vector

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