CY29972

Document #: 38-07290 Rev. *D

Page 3 of 13

Pin Configuration

VSS

MR#/OE

SCLK

SDATA

FB_SEL2

PLL_EN

REF_SEL

TCLK_SEL

TCLK0

TCLK1

XIN

XOUT

VDD

VSS

QB0

VDDC

QB1

VSS

QB2

VDDC

QB3

FB_IN

VSS

FB_OUT

VDDC

FB_SEL0

1

2

3

4

5

6

7

8

9

10

11

12

13

39

38

37

36

35

34

33

32

31

30

29

28

27

14 15 16 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 46 45 44 43 42 41 40

CY29972

Pin Description[2]

Pin

Name

PWR

I/O

Type

Description

11

–I

–

Oscillator input. Connect to a crystal.

12

–O

–

Oscillator output. Connect to a crystal.

–I

PU

External reference/test clock input.

10

–I

PU

External reference/test clock input.

44, 46, 48, 50

QA(3:0)

O–

Clock outputs. See Table 2 for frequency selections.

32, 34, 36, 38

QB(3:0)

O–

16, 18, 21, 23

QC(3:0)

O–

29

FB_OUT

O–

Feedback clock output. Connect to FB_IN for normal operation. The

divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page

1. A bypass delay capacitor at this output will control Input Reference/

Output Banks phase relationships.

25

SYNC

O–

Synchronous pulse output. This output is used for system

synchronization. The rising edge of the output pulse is in sync with both

the rising edges of QA (0:3) and QC(0:3) output clocks regardless of

the divider ratios selected.

42, 43

SELA(1,0)

–

I

PU

Frequency select inputs. These inputs select the divider ratio at

QA(0:3) outputs. See Table 2.

40, 41

SELB(1,0)

–

I

PU

Frequency select inputs. These inputs select the divider ratio at

QB(0:3) outputs. See Table 2.

19, 20

SELC(1,0)

–

I

PU

Frequency select inputs. These inputs select the divider ratio at

QC(0:3) outputs. See Table 2.

Note

2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their

high-frequency filtering characteristics will be cancelled by the lead inductance of the traces

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