TLE5012 datasheet(32/64 Pages) INFINEON

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TLE5012

Specifications

Final Data Sheet

V 1.0, 2010-11

Data Communication via SSC

Figure 20

SSC bit ordering (read example)

The data communication via SSC Interface has the following characteristics:

•

The data transmission order is “Most Significant Bit (MSB) first”.

•

Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.

•

The SSC Interface is word-aligned. All functions are activated after each transmitted word.

•

A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer

immediately. The CRC calculator is automatically reset.

•

After changing the data direction, a delay (twr_delay) has to occur before continuing the data transfer. This is

necessary for internal register access.

•

Every access to the TLE5012 with the number of data (ND) ≥ 1 is performed with address auto-increment. At

an overflow at address 3FH the transfer continuous at address 00H.

•

With ND = 0, no auto-increment is done and a continuously readout of the same address can occur. Afterwards

no Safety Word is sent and the transfer ends with high condition on CSQ.

•

After every data transfer with ND ≥ 1, the 16-bit Safety Word will be appended by the selected TLE5012.

•

After the Safety Word is sent, the transfer ends. To start another data transfer, the CSQ has to be deselected

once for tCSoff.

•

The SSC is by default push-pull. The push-pull driver is active only if the TLE5012 has to send data; otherwise

the push-pull is disabled for receiving data from the microcontroller.

Cyclic Redundancy Check (CRC)

•

This CRC complies with the J1850 Bus Specification.

•

Every new transfer resets the CRC generation.

•

Every byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).

•

Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast CRC generation circuit is used

(see Figure 21)

•

The remainder of the fast CRC circuit is initial set to ’11111111B’.

•

The remainder is inverted before transmission.

Figure 21

Fast CRC polynomial division circuit

SCK

DATA

MSB

CSQ

SSC Transfer

LSB

321

Command Word

Data Word (s)

SSC -Master is driving DAT A

SSC -Slave is driving DAT A

LSB

ADDR

LENGTH

LOCK

MSB

twr_delay

UPD

xor

Input

Serial

CRC

output

TX_CRC

1111

parallel

Remainder

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