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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADATE318 датащи(PDF) 64 Page - Analog Devices |
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ADATE318 датащи(HTML) 64 Page - Analog Devices |
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64 / 80 page  ADATE318 Rev. 0 | Page 64 of 80 tSPI 3µs tDAC NOTE 1 NOTE 1 ±0.5 LSB COMPLETION OF 3µs DEGLITCH PERIOD RETRIGGER OF 3µs DEGLITCH PERIOD BEGINNING OF 3µs DEGLITCH PERIOD NOTES 1. DAC DEGLITCH PERIOD ALWAYS BEGINS FOUR SCLK CYCLES BEFORE RELEASE OF BUSY. DAC23 DAC2 DAC1 DAC0 BUSY SDI CS SCLK SEE TABLE 18 WRITE DAC0 WRITE DAC1 SEE TABLE 18 Figure 126. SPI DAC Write and Settling Time Addressing M and C Registers Some DACs have pairs of m/c-coefficients that are controlled depending on other register status. Table 20 details the specific register settings and register addresses for the different pairs (X = don’t care). Table 20. M- and C-Register Mapping SPI Address (Channel) DAC Name Functional (DAC Usage) Description m- register c- register VHH_ ENABLE 0x18[0] DMC_ ENABLE 0x1C[0] LOAD_ ENABLEx 0x19[5] PPMU_ POWERx 0x1A[15] PPMU_ MEAS_ VIx 0x1A[5] PPMU_FORCE _VIx 0x1A[4] PPMU_ RANGEx (0x1A[3:1]) 0x0D[0] OVDL Overvoltage detect low 0x2D[0] 0x3D[0] X X X X X X XXX 0x04[0] VOH0 NWC high level, Channel 0 0x24[0] 0x34[0] X 0 X 0 X X XXX DMC high level 0x44[0] 0x5C[0] X 1 X 0 X X XXX PPMU go/no-go MV high level, Channel 0 0x45[0] 0x5D[0] X X X 1 0 X XXX PPMU go/no-go MI Range A high level, Channel 0 0x46[0] 0x5E[0] X X X 1 1 X 111 PPMU go/no-go MI Range B high level, Channel 0 0x47[0] 0x5E[0] X X X 1 1 X 110 PPMU go/no-go MI Range C high level, Channel 0 0x48[0] 0x5E[0] X X X 1 1 X 101 PPMU go/no-go MI Range D high level, Channel 0 0x49[0] 0x5E[0] X X X 1 1 X 100 PPMU go/no-go MI Range E high level, Channel 0 0x4A[0] 0x5E[0] X X X 1 1 X 0XX |
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