AD8553 datasheet(12/20 Pages) AD

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AD8426

Preliminary Technical Data

Rev. PrD | Page 12 of 20

Only the positive signal path is amplified; the negative path

is unaffected. This uneven amplification degrades the CMRR of

the amplifier.

INCORRECT

AD8426

VREF

CORRECT

AD8426

OP1177

–

VREF

CORRECT

AD8426

–

VREF

Figure 8. Driving the Reference Pin

INPUT VOLTAGE RANGE

The three op amp architecture of the AD8426 applies gain in the

first stage before removing common-mode voltage in the

difference amplifier stage. In addition, the input transistors in

the first stage shift the common-mode voltage up one diode

drop. Therefore, internal nodes between the first and second

stages (Node 1 and Node 2 in Figure 7) experience a combina-

tion of gained signal, common-mode signal, and a diode drop.

This combined signal can be limited by the voltage supplies even

when the individual input and output signals are not.

Equation 1 to Equation 3 can be used to understand how the

gain (G), common-mode input voltage (VCM), differential input

voltage (VDIFF), and reference voltage (VREF) interact. The values

for the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, at different temper-

atures are shown in Table 8. These three formulas, along with

the input and output range specifications in Table 2 and Table 3,

set the operating boundaries of the part.

LIMIT

DIFF











)

)(

(

(1)

LIMIT

DIFF











)

)(

(

(2)

LIMIT

REF

DIFF

)

)(

(









(3)

Table 8. Input Voltage Range Constants for Various

Temperatures

Temperature

V−LIMIT

V+LIMIT

VREF_LIMIT

−40°C

−0.55

+0.8

+1.3

+25°C

−0.35

+0.7

+1.15

+85°C

−0.15

+0.65

+1.05

+125°C

−0.05

+0.6

+0.9

The common-mode input voltage range shifts upward with temp-

erature. At cold temperatures, the part requires extra headroom

from the positive supply, whereas operation near the negative

supply has more margin. Conversely, at hot temperatures, the part

requires less headroom from the positive supply but is subject

to the worst-case conditions for input voltages near the negative

supply.

A typical part functions up to the boundaries described in this

section. However, for best performance, designing with a few

hundred millivolts extra margin is recommended. As signals

approach the boundary, internal transistors begin to saturate,

which can affect frequency and linearity performance.

LAYOUT

To ensure optimum performance of the AD8426 at the PCB

level, care must be taken in the design of the board layout.

The AD8426 pins are arranged in a logical manner to aid in

this task.

678

–IN1

+IN1

RG1

AD8426

–IN2

+IN2

RG2

Figure 9. Pinout Diagram

Package Considerations

The AD8426 is available in a 16-lead, 4 mm × 4 mm LFCSP with

no exposed paddle. The footprint from another 4 mm × 4 mm

LFCSP part should not be copied because it may not have the

correct lead pitch and lead width dimensions. Refer to the

Outline Dimensions section for the correct dimensions.

Hidden Paddle Package

The AD8426 is available in an LFCSP package with a hidden

paddle. Unlike chip scale packages where the pad limits routing

capability, this package allows routes and vias directly beneath

the chip, so that the full space savings of the small LFCSP can be

realized. Although the package has no metal in the center of the

part, the manufacturing process leaves a very small section of

exposed metal at each of the package corners, as shown in

Figure 10 and in Figure 17 in the Outline Dimensions section.

This metal is connected to –VS through the part. Because of the

possibility of a short, vias should not be placed underneath

these exposed metal tabs.

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