VPS12 Thermal Design Example

Conditions:

As was mentioned previously, the chip with the largest loss is Tr3 in the emitter-follower stage. Deriving that value from

the figures below and equation (3) gives:

Pc (EF stage) = 5.8

× 0.22 ≈ 1.3 [W] ............................................(5)

Next, applying the value of

θj-c to equation (5) shows ∆Tj to be as follows:

∆Tj = 1.3 × 35 = 45.5 [°C]

Here,

∆Tj is less than 50°C, and in the thermal design we only have to assure that Tc is less than 100°C. That is, we must

set

θh so that Tc is less than 100°C when Pd (TOTAL) = Pd (one channel) × 3.

Here,

∆Tc will be ∆Tc = 100 – 60 = 40°C

Since

θh = ∆Tc ÷ Pd (TOTAL) = 40 ÷ (5.8 × 3) = 2.3, then θh = 2.3 °C/W.

In an actual system, it may be possible to use a heat sink smaller than the one required for the value calculated above due

to the actual ambient temperature and other operating conditions. Actual designs should be optimized to match those

conditions using the data presented above.

No. 5309-4/4

VPS12

80

10

40

45

This catalog provides information as of September, 1996. Specifications and information herein are subject to

change without notice.

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