LTC4263 datasheet(23/32 Pages) LINER

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LTC4270/LTC4271

42701f

APPLICATIONS INFORMATION

Table 5. Example Current Limit Settings

ILIM (mA)

INTERNAL REGISTER SETTING (hex)

RSENSE = 0.5Ω

RSENSE = 0.25Ω

106

159

213

266

319

372

425

478

531

584

638

744

850

956

1063

1169

1275

1488

1700

1913

2125

2338

2550

2975

ILIM Foldback

The LTC4270/LTC4271 features a two-stage foldback circuit

that reduces the port current if the port voltage falls below

the normal operating voltage. This keeps MOSFET power

dissipation at safe levels for typical 802.3af MOSFETs,

even at extended 802.3at power levels. Current limit and

foldback behavior are programmable on a per-port basis.

Table 5 gives examples of recommended ILIM register

settings.

The LTC4270/LTC4271 will support current levels well

beyond the maximum values in the 802.3at specification.

The shaded areas in Table 5 indicate settings that may

require a larger external MOSFET, additional heat sinking,

or setting tLIM Enable.

MOSFET Fault Detection

LTC4270/LTC4271 PSE ports are designed to tolerate

significant levels of abuse, but in extreme cases it is pos-

sible for the external MOSFET to be damaged. A failed

MOSFET may short source to drain, which will make the

port appear to be on when it should be off; this condition

may also cause the sense resistor to fuse open, turning

off the port but causing the LTC4270 SENSE pin to rise

to an abnormally high voltage. A failed MOSFET may also

short from gate to drain, causing the LTC4270 GATE pin

to rise to an abnormally high voltage. The LTC4270 OUT,

SENSE and GATE pins are designed to tolerate up to 80V

faults without damage.

If the LTC4270/LTC4271 sees any of these conditions for

more than 180μs, it disables all port functionality, reduces

the gate drive pull-down current for the port and reports

a FET Bad fault. This is typically a permanent fault, but

the host can attempt to recover by resetting the port, or

by resetting the entire chip if a port reset fails to clear the

fault. If the MOSFET is in fact bad, the fault will quickly

return, and the port will disable itself again. The remaining

ports of the LTC4270/LTC4271 are unaffected.

An open or missing MOSFET will not trigger a FET Bad

fault, but will cause a tSTART fault if the LTC4270/LTC4271

attempts to turn on the port.

Port Current Readback

The LTC4270/LTC4271 measures the current at each port

with an internal A/D converter. Port data is only valid when

the port power is on and reads zero at all other times. The

converter has two modes:

• 100ms mode: Samples are taken continuously and the

measured value is updated every 100ms

• 1s mode: Samples are taken continuously; a moving 1

second average is updated every 100ms

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