300MHz to 450MHz Frequency-Programmable

ASK/FSK Transmitter

4

_______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(

Typical Application Circuit, 50

guaranteed by design and characterization over temperature, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SERIAL INTERFACE (SPI) TIMING CHARACTERISTICS (Figure 1)

Minimum SCLK Low to Falling-

Edge of

CS Setup Time

10

ns

Minimum

CS Low to Rising-Edge

of SCLK Setup Time

5ns

Minimum SCLK Low to Rising-

Edge of

CS Setup Time

20

ns

Minimum SCLK Low After Rising-

Edge of

CS Hold Time

5ns

Minimum Data Valid to SCLK

Rising-Edge Setup Time

10

ns

Minimum Data Valid to SCLK

Rising-Edge Hold Time

5ns

Minimum SCLK High Pulse Width

40

ns

Minimum SCLK Low Pulse Width

40

ns

Minimum

CS High Pulse Width

40

ns

Maximum Transition Time from

Falling-Edge of

CS to Valid GPO

DGND

50

ns

Maximum Transition Time from

Falling-Edge of SCLK to Valid

GPO

DGND

50

ns

Note 1: Supply current and output power are greatly dependent on board layout and PAOUT match.

Note 2: 50% duty cycle at 10kHz ASK data (Manchester coded).

Note 3: Guaranteed by design and characterization, not production tested.

Note 4: Dependent on PCB trace capacitance.

CS

SCLK

SDI

GPO

Figure 1. SPI Timing Diagram