R2A20124AFP/R2A20124ASP

Preliminary

R03DS0031EJ0300 Rev.3.00

Page 9 of 12

Mar 11, 2011

Electrical Characteristics (cont.)

(Ta = 25°C, Vcc = 12 V, RT = 180 k

, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.)

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

PHASE MODULATOR: R2A20124AFP/ASP

RAMP offset voltage

1.035

1.135

1.235

V

RAMP source current

–220

–185

–150

A

RAMP = 0.15 V, COMP; open

RAMP sink current

3

10

—

mA

RAMP = 0.15 V, COMP = 0 V

Minimum phase shift

Dmin

—

0*

—

%

RAMP = 0 V, COMP = 0 V

Maximum phase shift

Dmax

—

97.0*

—

%

RAMP = 0 V, COMP = 2.1 V

Delay to OUT-C, -D *

2

Tpd

—

100

200

ns

COMP = 1.6 V

RAMP discharge time *

1

Tdis

—

80

120

ns

FB(–) = 0.75 V, COMP; open

RAMP-SLP voltage

2.1

2.3

2.5

V

DELAY: R2A20124AFP/ASP

DELAY-1, -2 *

3

70

100

130

ns

Delay set R = 51 k



DELAY-3 *

3

45

65

85

ns

Delay set R = 51 k



DELAY2-1, -2 *

140

220

300

ns

Delay set R = 180 k



DELAY2-3 *

110

170

230

ns

Delay set R = 180 k



Terminal voltage

1.9

2.0

2.1

V

Delay set R = 51 k



SOFT START: R2A20124AFP/ASP

Source current

–14

–10

–6

A

SS = 1 V

SS high voltage

3.9

4.0

4.1

V

Notes: 1. Design specification (reference data)

2. Tpd is defined as;

RAMP

OUT-C/D

Tpd

0 V

1 V

50%

50%

VCC

0 V

OUT-A

OUT-B

OUT-C

OUT-D

OUT-E

OUT-F

50%

For primary

control

For secondary

control

4. Maximum/Minimum phase shift is defined as;

T1

T1

T2

OUT-A

OUT-D

T2

OUT-B

OUT-C

D =

× 2 × 100 (%)

T2

T1