LPC1763 datasheet(39/79 Pages) NXP

39 / 79 page

LPC1769_68_67_66_65_64_63

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Product data sheet

Rev. 7 — 5 April 2011

39 of 79

NXP Semiconductors

LPC1769/68/67/66/65/64/63

32-bit ARM Cortex-M3 microcontroller

7.30 System control

7.30.1 Reset

Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains

a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see

description in Section 7.29.5). The wake-up timer ensures that reset remains asserted

until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks

have passed, and the flash controller has completed its initialization. Once reset is

de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD

threshold, the RSTOUT pin goes HIGH.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

Fig 6.

Power distribution

REAL-TIME CLOCK

BACKUP REGISTERS

REGULATOR

32 kHz

OSCILLATOR

RTC POWER DOMAIN

MAIN POWER DOMAIN

002aad978

RTCX1

VBAT

VDD(REG)(3V3)

RTCX2

VDD(3V3)

VSS

to memories,

peripherals,

oscillators,

PLLs

to core

to I/O pads

ADC

DAC

ADC POWER DOMAIN

VDDA

VREFP

VREFN

VSSA

LPC17xx

ULTRA LOW-POWER

REGULATOR

POWER

SELECTOR

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