SL811HS

Document 38-08008 Rev. *F

Page 13 of 32

Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h.

SOF Counter High/Control Register 2 [Address = 0Fh]. When read, this register returns the value of the SOF counter divided by

64. The software must use this register to determine the available bandwidth in the current frame before initiating any USB transfer.

In this way, the user is able to avoid babble conditions on the USB. For example, to determine the available bandwidth left in a frame

do the following.

Maximum number of clock ticks in 1 ms time frame is 12000 (1 count per 12 MHz clock period, or approximately 84 ns.) The value

read back in Register 0FH is the (count × 64) × 84 ns = time remaining in current frame. USB bit time = one 12 MHz period.

Value of register 0FH

Available bit times left are between

BBH

12000 bits to 11968 (187 × 64) bits

BAH

11968 bits to 11904 (186 × 64) bits

Note: Any write to the 0Fh register clears the internal frame counter. Write register 0Fh at least once after power-up. The internal

frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which is used to track the

frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave every millisecond in

a SOF packet.

When writing to this register the bits definition are defined as follows.

Note Any write to Control register 0Fh enables the SL811HS full

features bit. This is an internal bit of the SL811HS that enables

additional features.

The USB-B register set is used when SL811HS full feature bit is

enabled.

Example. To set up host to generate 1 ms SOF time:

The register 0Fh contains the upper 6 bits of the SOF timer.

Register 0Eh contains the lower 8 bits of the SOF timer. The

timer is based on an internal 12 MHz clock and uses a counter,

which counts down to zero from an initial value. To set the timer

for 1 ms time, the register 0Eh is loaded with value E0h and

register 0Fh (bits 0–5) is loaded with 2Eh. To start the timer, bit

0 of register 05h (Control Register 1) is set to ’1’, which enables

hardware SOF generation. To load both HIGH and LOW

registers with the proper values, the user must follow this

sequence:

1. Write E0h to register 0Eh. This sets the lower byte of the SOF

counter

2. Write AEh to register 0Fh, AEh configures the part for full

speed (no change of polarity) Host with bits 5–0 = 2Eh for

upper portion of SOF counter.

3. Enable bit 0 in register 05h. This enables hardware generation

of SOF.

4. Set the ARM bit at address 00h. This starts the SOF

generation.

Table 16. SOF Counter LOW Address when Written [Address 0Eh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SOF7

SOF6

SOF5

SOF4

SOF3

SOF2

SOF1

SOF0

Table 17. SOF High Counter when Read [Address 0Fh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C13

C12

C11

C10

C9

C8

C7

C6

Table 18. Control Register 2 when Written [Address 0Fh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SL811HS

Master/Slave

selection

SL811HS

D+/D– Data

Polarity Swap

SOF High Counter Register

Bit Position

Bit Name

Function

7

SL811HS Master/Slave selection

Master = 1, Slave = 0.

6

SL811HS D+/D– Data Polarity Swap

’1’ = change polarity (low speed)

’0’ = no change of polarity (full speed).

5-0

SOF High Counter Register

Write a value or read it back to SOF High Counter Register.

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