CY8C52 datasheet(3/94 Pages) CYPRESS

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PRELIMINARY

PSoC® 5: CY8C52 Family Datasheet

Document Number: 001-66236 Rev. **

Page 3 of 94

1. Architectural Overview

Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

Figure 1-1 on page 3 illustrates the major components of the

CY8C52 family. They are:

ARM Cortex-M3 CPU subsystem

Nonvolatile subsystem

Programming, debug, and test subsystem

Inputs and outputs

Clocking

Power

Digital subsystem

Analog subsystem

PSoC’s digital subsystem provides half of its unique

configurability. It connects a digital signal from any peripheral to

any pin through the digital system interconnect (DSI). It also

provides functional flexibility through an array of small, fast, low

power UDBs. PSoC Creator provides a library of pre-built and

tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,

timer, counter, PWM, AND, OR, and so on) that are mapped to

the UDB array. The designer can also easily create a digital

circuit using boolean primitives by means of graphical design

entry. Each UDB contains programmable array logic

(PAL)/programmable logic device (PLD) functionality, together

with a small state machine engine to support a wide variety of

peripherals.

Digital

Filter

Block

LCD Direct

Drive

CapSense

Temperature

Sensor

4 x

Opamp

ADCs

4x DAC

1 x

Del Sig

ADC

4 x SC / CT Blocks

(TIA, PGA, Mixer etc)

4 x

CMP

Program

Debug&

Trace

Boundary

Scan

Program &

Debug

8051or

Cortex M3CPU

Interrupt

Controller

PHUB

DMA

Cache

Controller

SRAM

FLASH

EEPROM

EMIF

Digital Interconnect

Analog Interconnect

0. 5 to5.5 V

( Optional)

4- 25 MHz

( Optional)

Xtal

Osc

32.768 KHz

( Optional)

RTC

Timer

IMO

WDT

and

Wake

ILO

Clocking System

1.8 V LDO

SMP

POR and

LVD

Sleep

Power

Power Management

System

USB

PHY

3 per

Opamp

2 x

SAR

ADC

CAN

2.0

I2C

Master/

Slave

Universal Digital Block Array (24 x UDB)

4 x

Timer

Counter

PWM

FS USB

2.0

UDB

UART

Logic

12- Bit PWM

I2C Slave

8- Bit SPI

12- Bit SPI

Logic

8- Bit

Timer

16- Bit PRS

UDB

8- Bit

Timer

Quadrature Decoder

16- Bit

PWM

UDB

Memory System

CPU System

Analog System

System Bus

Digital System

System Wide

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