©2011 Silicon Storage Technology, Inc.

S71327-04-000

02/11

17

32 Mbit SPI Serial Flash

SST25VF032B

Data Sheet

A Microchip Technology Company

Chip-Erase

The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored

if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction

must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.

Initiate the Chip-Erase instruction by executing an 8-bit command, 60H or C7H. CE# must be driven high

tion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase sequence.

Figure 15:Chip-Erase Sequence

Read-Status-Register (RDSR)

The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register

may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in

progress, the Busy bit may be checked before sending any new commands to assure that the new

commands are properly received by the device. CE# must be driven low before the RDSR instruction is

entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing

clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR

instruction sequence.

Figure 16:Read-Status-Register (RDSR) Sequence

CE#

SO

SI

SCK

01 2 3 4 5 6 7

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

1327 F16.0

MSB

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1327 F17.0

MODE 3

SCK

SI

SO

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05

MODE 0

HIGH IMPEDANCE

Status

Register Out

MSB

MSB