MCP3301T datasheet(17/38 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS21700D-page 17

MCP3301

5.0

APPLICATIONS INFORMATION

5.1

Conversion Description

The MCP3301MCP3301 A/D converter employs a con-

ventional SAR architecture. With this architecture, the

potential between the IN+ and IN- inputs are

simultaneously sampled and stored with the internal

sample circuits for 1.5 clock cycles (tACQ). Following

this sample time, the input hold switches of the

converter open and the device uses the collected

charge to produce a serial 13-bit binary two’s

complement output code. This conversion process is

driven by the external clock and must include 13 clock

cycles, one for each bit. During this process, the most

significant bit (MSB) is output first. This bit is the sign

bit and indicates whether the IN+ input or the IN- input

is at a higher potential.

FIGURE 5-1:

Simplified Block Diagram.

5.2

Driving the Analog Input

The analog input of the MCP3301 is easily driven either

differentially or single-ended. Any signal that is

common to the two input channels will be rejected by

the common mode rejection of the device. During the

charging time of the sample capacitor, a small charging

current will be required. For low source impedances,

this input can be driven directly. For larger source

impedances, a larger acquisition time will be required,

due to the RC time constant that includes the source

impedance. For the A/D Converter to meet specifica-

tion, the charge holding capacitor (CSAMPLE) must be

given enough time to acquire a 13-bit accurate voltage

level during the 1.5 clock cycle acquisition period.

An analog input model is shown in Figure 5-3. This

model is accurate for an analog input, regardless of

whether it is configured as a single-ended input or the

IN+ and IN- input in differential mode. In this diagram,

it is shown that the source impedance (RS) adds to the

internal sampling switch (RSS) impedance, directly

affecting the time that is required to charge the capaci-

tor (CSAMPLE). Consequently, a larger source imped-

ance with no additional acquisition time increases the

offset, gain, and integral linearity errors of the conver-

sion. To overcome this, a slower clock speed can be

used to allow for the longer charging time. Figure 5-2

shows the maximum clock speed associated with

source impedances.

FIGURE 5-2:

Maximum Clock Frequency

vs. Source Resistance (RS) to maintain ±1 LSB

INL.

Shift

Comp

13-Bit SAR

CDAC

IN+

IN-

CSAMP

Hold

CSAMP

DOUT

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

100

1000

10000

100000

Input Resistance (ohms)

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