LC07424LP

7. SP AMP

This is the monaural speaker amplifier. Its maximum output is 250mW (typ VDD =2.8V, 8Ω, THD+N = 10%).

This amplifies the MIX circuit output. EVR (+0dB to -65.2dB) is mounted.

A thermal shutdown function is provided. When it is left enabled, the speaker amplifier operation is automatically

shut down when the chip temperature has reached a high level.

8. Video driver

Either the sag compensation type or DC direct coupling type is selectable.

The gain adjustment circuit (6.5dB±1.7dB, 0.1dB/step) is mounted.

9. Register settings

This is a 3-line system serial control circuit. The three lines are CS_X (Chip Select/low active), SCLK (Serial Clock)

and SDin (Serial Data). Data can only be written into the register: The register data cannot be read out.

The data transfer rate—in other words, the maximum SCLK frequency—depends on the MCLK pin clock. For

details, refer to the section “Switching characteristics.”

10. Master clock

The master clock frequency is 256fs. This clock signal must be input from the MCLK pin.

11. Audio data formats

BCLK and LRCLK. For details, refer to the section “Audio data formats.”

Microcontroller Serial Interface

The internal registers values are written by the serial interface consisting of the three CS_X, SCLK, and SDin lines.

When the CS_X pin is set low, the LC07424LP is switched into the mode that enables operation. The data is received

on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1

are accessed in sequence with each byte following access to the register specified by the address byte.

If the size of data exceeding the highest address (1Dh) is accessed in this process, the data concerned is treated as

invalid. In other word, the address never wraps around to 00 (HEX). The maximum data transfer rate (maximum SCLK

frequency) depends on the MCLK pin clock. Refer to the section "Switching characteristics."

CS_X

SCLK

SDin

WRITE DATA (address A)

ADDRESS BYTE

X

X

X

X

X

X

A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

A [7:0] : Designated address

D [7:0] : Register data

X

: Invalid

Transferring data to one address

Data (D) is written in address (A)

CS_X

SCLK

SDin

WRITE DATA (address A)

ADDRESS BYTE

WRITE DATA (address A+1)

D

D

D

D

D

D

D

D

A

A

A

g

A

A

A

D

D

D

D

D

D

D

D

D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0]

Dn[0]

X

X

X

X

D

D1[7]D1[6]D1[5]D1[4]D1[3]D1[2]D1[1]D1[0]

A

A[6] A[5] A[4] A[3] A[2] A[1] A[0]

A[7]

Transferring data to contiguous addresses

Data (D0) is written in address (A), and data (D1) is written into address (A+1).

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