CY23FS08

Document Number: 38-07518 Rev. *F

Page 3 of 15

Pinouts

Figure 1. Pin Configuration

CLKB1

S2

S3

VDDB

CLKB2

S4

VDDB

XIN

VDDC

FAIL#/SAFE

28

27

26

25

24

23

22

21

1

2

3

4

5

6

7

8

28-pin SSOP

REF1

REF2

VSSB

REFSEL

FBK

VSSA

CLKA1

CLKA2

S1

VDDA

9

10

11

12

13

14

VSSB

CLKB3

CLKB4

20

19

18

17

16

15

VSSA

CLKA3

CLKA4

VDDA

XOUT

Notes

1. For normal operation, connect either one of the eight clock outputs to the FBK input.

2. Weak pull downs on all CLK outputs.

3. Weak pull ups on these inputs.

4. Weak pull downs on these inputs.

Table 1. Pin Definitions

Pin Number

Pin Name

Description

1,2

REF1,REF2

Reference clock inputs.[4] 5 V tolerant.

4,5,10,11

CLKB[1:4]

Bank B clock outputs.[1, 2]

25,24,19,18

CLKA[1:4]

Bank A clock outputs.[1, 2]

27

FBK

Feedback input to the PLL.[1]

23,6,7,22

S[1:4]

Frequency select pins/PLL and DCXO bypass.[3]

14

XIN

Reference crystal input.

15

XOUT

Reference crystal output.

16

FAIL#/SAFE

Valid reference indicator. A high level indicates a valid reference input.

13

VDDC

3.3 V power supply for the internal circuitry.

8,12

VDDB

2.5 V or 3.3 V power supply for Bank B outputs.

3,9

VSSB

Ground.

17,21

VDDA

2.5 V or 3.3 V power supply for Bank A outputs.

20,26

VSSA

Ground.

28

REFSEL

Reference select. Selects the active reference clock from either REF1 or REF2.

When REFSEL = 1, REF1 is selected. When REFSEL = 0, REF2 is selected.

Table 2. Configuration Table

S[4:1]

XTAL (MHz)

REF(MHz)

OUT(MHz)

REF:OUT

Ratio

REF:XTAL

Ratio

Out:XTAL Ratio

Min

Max

Min

Max

Min

Max

0000

PLL and DCXO Bypass mode

1000

8.33

30

16.67

60.00

8.33

30.00

22

1

1110

9.50

30

57.00

180.00

28.50

90.00

26

3

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