33882 datasheet(17/27 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33882

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33882 incorporates six 1.0 A low-side switches using

both Serial Peripheral Interface (SPI) I/O as well as optional

parallel input control to each output. There are also two low-

power (30 mA) low-side switches with SPI diagnostic

feedback, but parallel-only input control. The 33882

incorporates SMARTMOS technology with CMOS logic,

bipolar/MOS analog circuitry, and DMOS power MOSFETs.

Designed to interface directly with a microcontroller, it

controls inductive or incandescent loads. Each output is

configured as an open drain transistor with dynamic

clamping.

FUNCTIONAL PIN DESCRIPTION

VPWR Pin

The VPWR pin is connected to battery voltage. This supply

is provided for overvoltage shutdown protection and for

added gate drive capabilities. A decoupling capacitor is

required from VPWR to ground.

IN0 & IN1, IN2 & IN3, and IN4 & IN5 Pins

These input pins control two output channels each when

the MODE pin is pulled high: IN0 & IN1 controls OUT0 and

OUT1, IN2 & IN3 controls OUT2 and OUT3, while IN4 & IN5

controls OUT4 and OUT5. These pins may be connected to

PWM outputs of the control IC and pulled high or pulled low

to control output channel states while the MODE pin is high.

The states of these pins are ignored during normal operation

(MODE pin low) and override the normal inputs (serial or

parallel) when the MODE pin is high. These pins have internal

active 25

μA pull-downs.

MODE Pin

The MODE pin is connected to the MODE pin of the control

IC. This pin has an internal active 25

μA pull-up. When pulled

high, the MODE pin does the following:

• Disables all serial control of the outputs while still reading

any serial input commands.

• Disables parallel inputs IN0, IN1, IN2, IN3, IN4, and IN5

control of the outputs.

• Selects IN0 & IN1, IN2 & IN3, and IN4 & IN5 input pins for

control of OUT0 and OUT1, OUT2 and OUT3, OUT4 and

OUT5, respectively.

• Turns off OUT6 and OUT7.

• Tri-states the SO pin.

IN0 to IN7 Pins

These are parallel input pins connected to output pins of

the control IC. Each parallel input is logic high with the

corresponding SPI control bit to control each output channel.

These pins have internal 25

μA active pull-downs.

OUT0 to OUT7 Pins

Each pin is one channel's low-side switch output. OUT0 to

OUT5 are actively clamped to handle inductive loads.

SI Pin

The Serial Input pin is connected to the SPI Serial Data

Output pin of the control IC from where it receives output

command data. This input has an internal active 25

μA pull-

down and requires CMOS logic levels. The serial data

transmitted on this line is an 8- or 16-bit control command

sent MSB first, controlling the six output channels. Bits A5

through A0 control channels 5 through 0, respectively. Bits

A6 and A7 enable ON open load fault detection on channels

5 through 0. The control IC will ensure that data is available

on the rising edge of SCLK. Each channel has its serial

control bit high with its parallel input to determine its state.

SCLK Pin

The SCLK pin of the control IC is a bit (shift) clock for the

SPI port. It transitions one time per bit transferred when in

operation. It is idle between command transfers. It is 50%

duty cycle and has CMOS levels. This signal is used to shift

data to and from the device. For proper fault reporting

operation, the SCLK input must be low when CS transitions

from high to low.

CS Pin

The CS pin is connected to a chip select output of the

control IC. The control IC controls which device is addressed

by pulling the CS pin of the desired device low, enabling the

SPI communication with the device, while other devices on

the serial link keep their serial outputs tri-stated. This input

has an internal active 25

μA pull-up and requires CMOS logic

levels.

SO Pin

The Serial Output pin is connected to the SPI Serial Data

Input pin of the control IC or to the SI pin of the next device in

a daisy chain. This output will remain tri-stated unless the

device is selected by a low CS pin or the MODE pin goes low.

The output signal generated will have CMOS logic levels and

the output data will transition on the falling edges of SCLK.

The serial output data provides fault information for each

output and is returned MSB first when the device is

addressed. Fault bit assignments for return data are as

follows: MSB-0 through MSB-7 are output fault bits for OUT7

to OUT0, respectively. In 8-bit SPI mode, under normal

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