CY2DM1502 datasheet(11/12 Pages) CYPRESS

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CY2DM1502

Document Number: 001-56315 Rev. *F

Page 11 of 12

Document History Page

Document Title: CY2DM1502 1:2 CML / LVPECL Input to CML Output Fanout Buffer

Document Number: 001-56315

Revision

ECN

Orig. of

Change

Submission

Date

Description of Change

2782891

CXQ

10/09/09

New Datasheet.

2838916

CXQ

01/05/2010

Changed status from “ADVANCE” to “PRELIMINARY”.

Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page

1 and in tJIT in the AC Electrical Specs table on page 4.

Added tPU spec to the Operating Conditions table on page 2.

Removed VOH spec maximum of VDD in the DC Electrical Specs table on page

Changed VOL spec min from VDD - 0.6V to VDD - 0.7V; changed max from VDD

- 0.4V to VDD - 0.3V in the DC Electrical Specs table on page 3.

Removed VOD spec of minimum 300 mV, maximum 450 mV in the DC

Electrical Specs table on page 3.

Added RP spec in the DC Electrical Specs table on page 3. Min = 60 kΩ, Max

= 140 k

Ω.

Added a measurement definition for CIN in the DC Electrical Specs table on

page 3.

Added VPP spec to the AC Electrical Specs table on page 4. VPP max = 700

mV for DC - 150 MHz and max = 600 mV for 150 MHz to 1.5 GHz. VPP min =

250 mV over the entire range.

Changed letter case and some names of all the timing parameters in the AC

Electrical Specs table on page 4 to be consistent with EROS.

Lowered all additive phase noise mask specs by 3 dB in in the AC Electrical

Specs table on page 4.

Added condition to tR and tF specs in the AC Electrical specs table on page 4

that input rise/fall time must be less than 1.5 ns (20% to 80%).

Changed letter case and some names of all the timing parameters in Figures

3, 4, 5, 6 and 8, to be consistent with EROS.

3011766

CXQ

08/20/2010

Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page

1 and in tJIT in the AC Electrical Specs table.

Added note 3 to describe IIH and IIL specs.

Removed reference to data distribution from “Functional Description”.

Changed RP for diff inputs from 100 kΩ to 150 kΩ in the Logic Block Diagram

and from 60 k

Ω min / 140 kΩ max to 90 kΩ min / 210 kΩ max in the DC

Electrical Specs table.

Added max VID of 1.0V in DC Electrical Specs table.

Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to

-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical

Specs table.

Added “Frequency range up to 1 GHz” condition to tODC spec.

Updated package diagram.

Added Acronyms and Ordering Code Definition.

3017258

CXQ

08/27/2010

Corrected Output Rise/Fall time diagram.

3100234

CXQ

11/18/2010

Updated Phase jitter to 0.15ps max from 0.11ps max.

Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”

Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec

JESD78B IC Latchup Test”

Removed RP spec for differential input clock pins INX and INX#.

Changed CIN condition to “Measured at 10 MHz”.

Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets.

Added condition “Measured at 1 GHz” to tR, tF specs.

3137726

CXQ

01/13/2011

Removed “Preliminary” status heading.

Removed resistors from IN/IN# in Logic Block Diagram.

3090938

CXQ

02/25/2011

Post to external web.

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