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SC4525DEVB датащи(PDF) 15 Page - Semtech Corporation

номер детали SC4525DEVB
подробное описание детали  18V, 3A, 350kHz Step-Down Switching Regulator
PDF  21 Pages
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производитель  SEMTECH [Semtech Corporation]
домашняя страница  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC4525DEVB датащи(HTML) 15 Page - Semtech Corporation

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© 2011 Semtech Corp.
www.semtech.com
SC4525D
15
Applications Information (Cont.)
(13)
The temperature rise of the SC4525D is the product of the
total power dissipation (Equation (13)) and q
JA (36
o
C/W),
which is the thermal impedance from junction to ambient
for the SOIC-8 EDP package.
It is not recommended to operate the SC4525D above
125oC junction temperature.
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation,thesizeoftheloopformedbythesecomponents
should be minimized. Since the power switch is already
integrated within the SC4525D, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
O
C E S AT
C
I
V
D
P
⋅
⋅
=
40
I
V
D
P
O
B S T
B S T
⋅
⋅
=
DC
2
O
IND
R
I
)
3
.
1
~
1
.
1
(
P
⋅
⋅
=
O
D
D
I
V
)
D
1
(
P
⋅
⋅
−
=
S W
O
IN
S
S W
F
I
V
t
2
1
P
⋅
⋅
⋅
⋅
=
Q
B S T
S W
C
T OT AL
P
P
P
P
P
+
+
+
=
mA
2
V
P
IN
Q
⋅
=
O
C E S AT
C
I
V
D
P
⋅
⋅
=
40
I
V
D
P
O
B S T
B S T
⋅
⋅
=
DC
2
O
IND
R
I
)
3
.
1
~
1
.
1
(
P
⋅
⋅
=
O
D
D
I
V
)
D
1
(
P
⋅
⋅
−
=
S W
O
IN
S
S W
F
I
V
t
2
1
P
⋅
⋅
⋅
⋅
=
Q
B S T
S W
C
T OT AL
P
P
P
P
P
+
+
+
=
mA
2
V
P
IN
Q
⋅
=
Figure 9. Heavy lines indicate the critical pulse
current loop. Thes stray inductance of this
loop should be minimized.
Vout
Vin
+
+
Currents in Power Section
IN
V
OUT
V
L
Z
Vout
Vin
+
+
Currents in Power Section
IN
V
OUT
V
L
Z



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