SC197EVB datasheet(13/20 Pages) SEMTECH

13 / 20 page

SC197

lower will simplify the design. If I

LEAK is neglected and RFB2

is fixed, R

FB1 can be determined using the equation.

SET

OUT

Inserting resistance in the feedback loop will adversely

affect the system’s transient performance if feed-forward

capacitance is not included in the circuit. The circuit in

Figure 1 illustrates how the resistor divider and feed-

forward capacitor can be added to the SC197 schematic.

The value of feed-forward capacitance needed can be

determined using the equation.

SET

OUT

SET

SC197

INA

CTL3A

CTL2A

CTL1A

CTL0A

LXA

OUTA

GNDA

VOUT

VIN

COUT

CIN

Enable

CFF

RFB1

RFB2

Figure 1 — Application Circuit with External Resistors

To simplify the design, it is recommended to program the

output setting to 1.0V, use resistor values smaller than

10kΩ, and include a feed-forward capacitance calculated

with the equation above. If the output voltage is set to

1.0V, the previous equation reduces to the following.

OUT

Example:

An output voltage of 1.3V is desired, but this is not a pro-

grammable option. What external component values for

Figure 1 are needed?

Solution: To keep the circuit simple, set R

FB2 to 10kΩ so

current into the OUT(A/B) pin can be neglected and set

the CTL3-0 pins to 0010 (1.0V setting). The necessary

component values are as follows:

SET

OUT

PWM Operation

Normal PWM operation occurs when the output load

current exceeds the PSAVE threshold. In this mode, the

PMOS high side switch is activated with the duty cycle

required to produce the output voltage programmed by

the CTLx(A/B) pins. An internal synchronous NMOS recti-

fier eliminates the need for an external Schottky diode on

the LX(A/B) pin. The duty cycle (percentage of time PMOS

is active) increases as V

IN decreases to maintain output

voltage regulation. As the input voltage approaches the

programmed output voltage, the duty cycle approaches

100% (PMOS always on) and the device enters a pass-

through mode. This mode remains active until the input

voltage increases or the load decreases enough to allow

PWM switching to resume.

Power Save Mode Operation

When the load current decreases below the PSAVE

threshold, PWM switching stops and the device auto-

matically enters PSAVE mode. This threshold varies

depending on the input voltage and output voltage

setting, optimizing efficiency for all possible load currents

in PWM or PSAVE mode. While in PSAVE mode, output

voltage regulation is controlled by a series of switching

bursts. During a burst, the inductor current is limited to a

peak value which controls the on-time of the PMOS

switch. After reaching this peak, the PMOS switch is dis-

abled and the inductor current decreases to near 0mA.

Switching bursts continue until the output voltage climbs

to V

OUT +2.5% or until the PSAVE current limit is reached.

Switching is then stopped to eliminate switching losses,

enhancing overall efficiency. Switching resumes when

the output voltage reaches the lower threshold of V

OUT

and continues until the upper threshold again is reached.

Note that the output voltage is regulated hysteretically

while in PSAVE mode between V

OUT and VOUT + 2.5%. The

Applications Information (continued)

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